Patents by Inventor Kenneth H. Marz

Kenneth H. Marz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self test apparatus for identifying partially defective memory
    Patent number: 8055960
    Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: William V Huott, David J Lund, Kenneth H Marz, Bryan L Mechtly, Pradip Patel
  • Self Test Apparatus for Identifying Partially Defective Memory
    Publication number: 20090204762
    Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, David J. Lund, Kenneth H. Marz, Bryan L. Mechtly, Pradip Patel
  • Self test method and apparatus for identifying partially defective memory
    Patent number: 7366953
    Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, David J. Lund, Kenneth H. Marz, Bryan L. Mechtly, Pradip Patel