Abstract: Presently disclosed is an apparatus and method for returning control of bandwidth allocation and packet scheduling to the routing engine in a network communications device containing an ATM interface. Virtual circuit (VC) flow control is augmented by the addition of a second flow control feedback signal from each virtual path (VP). VP flow control is used to suspend scheduling of all VCs on a given VP when traffic has accumulated on enough VCs to keep the VP busy. A new packet segmenter is employed to segment traffic while preserving the first in, first out (FIFO) order in which packet traffic was received. Embodiments of the invention may be implemented using a two-level (per-VC and per-VP) scheduling hierarchy or may use as many levels of flow control feedback-derived scheduling as may be necessitated by multilevel scheduling hierarchies.

Abstract: A technique non-disruptively recovers from a processor failure in a multi-processor flow device, such as an intermediate network node of a computer network. Data relating to a particular data flow of a processor within the node is tagged with specific information used to detect and recover from a failure of the processor without affecting data from other processors of the node. A data path management device tags the data with the specific information reflecting the processor issuing the data and a state of the processor. When the tagged data subsequently passes through the data path management device, the specific information is compared with current information for the issuing processor. If the comparison indicates that the specific information is valid, the data path management device forwards the related data flow through the node. If the comparison indicates that the specific information is invalid, the data and its related data flow are discarded and “cleanly” purged from the node.

Abstract: In one embodiment a set of threads are assigned in a particular order to an order group. The first assigned thread is treated as being, at least initially, at a head-of-line (HOL) for the order group. Each thread of the set is assigned a separate sequence number, each sequence number indicating the order in which the respective thread was assigned to the order group. A given thread is prevented from performing at least some of the given thread's instruction sequence until the given thread reaches the HOL of the order group as indicated by a modifiable HOL sequence value.

Abstract: A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.

Abstract: A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a “free” buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.

Abstract: A buffer-management technique efficiently manages a set of data buffers accessible to first and second devices interconnected by a split transaction bus, such as a Hyper-Transport (HPT) bus. To that end, a buffer manager controls access to a set of “free” buffer descriptors, each free buffer descriptor referencing a corresponding buffer in the set of data buffers. Advantageously, the buffer manager ensures that the first and second devices are allocated a sufficient number of free buffer descriptors for use in a HPT data path protocol in which the first and second devices have access to respective sets of free buffer descriptors. Because buffer management over the HPT bus is optimized by the buffer manager, the amount of processing bandwidth traditionally consumed managing descriptors can be reduced.

Abstract: The present invention comprises a scheduling assist function (scheduling assist) that enables a processor to schedule events and be notified when these events expire. In addition, the present invention includes features that enable a processor to associate these events with output channels and enable the processor to quickly locate output channels (links) that are available and ready to be serviced. The invention takes advantage of the fact that the scheduling assist can be dedicated exclusively to scanning tables in its own dedicated memories looking for events that have expired and/or output channels that are available and not involve the processor in the search for output channels that are available and ready to be serviced.

Abstract: A system and method maintains order among a plurality of threads in a multi-threaded processing system. The processing system, which may be disposed at an intermediate network device, has a plurality of processors each supporting a plurality of threads. The ordering system includes a dispatcher that assigns work, such as the processing of received packets to free threads, an order manager that keeps track of the relative order of the threads, and a thread client associated with each thread for enforcing the determined order. Packets to be processed by the processing system are assigned to an initial order group by the order manager based on a selected attribute, and those packets sharing the same attribute value are assigned to the same order group. During processing, a thread may request reassignment to other order groups in response to other attributes of the packets.

Abstract: A technique efficiently transports token ring (TR) frames over trunks interconnecting switches of a distributed TR bridge. The TR bridge is characterized by a logical switch fabric that is distributed among the interconnected switches by the trunks, which are preferably interswitch link (ISL) trunks. Each switch includes a Bridge Relay Function (BRF) coupled to a plurality of Concentrator Relay Functions (CRFs) having a plurality of ports for receiving TR frames over TR segments. The BRF and CRF of the distributed TR bridge operate according to a 2-tier switching model wherein each CRF and BRF is assigned an individual virtual local area network identifier. The technique encapsulates the TR frames in a TR-ISL protocol format that accomodates differences in formats of various TR frames and that comports with the 2-tier switching model of the distributed TR bridge.

Abstract: A Distributed Ring Protocol (DRiP) arrangement includes a database and protocol for maintaining and distributing information within a distributed token ring (TR) bridge having a logical switch fabric that is distributed over a TR switching network of switches interconnected by trunk links, such as Inters witch Link (ISL) trunks. The DRiP information is used by switches within the ISL switched fabric to determine the status (configured and/or activated) and association (within a switch) of ports of the distributed bridge.

Abstract: A backup CRF VLAN arrangement provides an alternate, redundant path for traffic between undistributed Concentrator Relay Functions (CRFs) located on separate switches interconnected by trunk links of a distributed token ring bridge. The backup CRF virtual local area network (VLAN) arrangement defines a backup network path which may be utilized if a primary active path is not a valid path to a backup network. Notably, the backup network comprises a special type of CRF that is distributed among the switches, but that has only one port active at any given time.

Abstract: A distributed token ring (TR) bridge has a logical switch fabric that is distributed over a TR switching network of switches interconnected by trunk links. The distributed TR bridge includes a plurality of TR switches, each having a Bridge Relay Function (BRF) logically coupled to at least one Concentrator Relay Function (CRF). Distribution of the switch fabric essentially comprises logically distributing the BRF function among the network of switches.

Abstract: A LAN interconnect device includes a plurality of Frame Processing Units (FPUs) for coupling each port of the device to a switch fabric. Each one of the Frame Processing Units includes an input section with input logic which prepares LS Headers and appends each one to a block of the frame as the block is forwarded to the switch fabric. The FPU, also, includes an output section with copy logic for copying and assembling frames to be forwarded to devices connected to the port. The copy decision is based upon the LS Header and configuration information in the port.

Abstract: A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.

Abstract: An improved spanning tree protocol for use by token ring intermediate devices having one or more Concentrator Relay Function (CRF) entities and associated Bridge Relay Function (BRF) entities. Each CRF and BRF entity preferably includes a spanning tree engine and corresponding database for individually executing an instance of the spanning tree algorithm and is configured to select a different Bridge Protocol Data Unit (BPDU) message type for use in executing its respective spanning tree algorithm. The selection of BPDU message type by the CRF and BRF spanning tree engines preferably depends on the routing configuration of the associated CRF. The selection of BPDU message type by the CRF entities assures that they are dropped by legacy intermediate devices and only acted upon by the originating CRF or another CRF coupled thereto.

Abstract: A device for interconnecting Local Area Networks (LANs) includes ports for attaching LAN segments and port modules for connecting the ports to a switch fabric. Each of the port modules include a mechanism which searches the Routing Information (RI) field of a Received frame to detect at least two Triplets (a minimum configuration for a LAN segment) indicating a Source path from an originator user and a Destination path to a destination user. The Triplet (single or in combination) is used to access a database (tables) which identifies the Port of Exit (POE) through which the frame is to be routed.

Abstract: Controller triple modular redundancy is substantially achieved and reliability improved in a system having duplicate controllers that serve peripheral units. Both controllers detect suspected faults in itself and in the other controller. A peripheral unit that suspects a faulty active controller requests a switch of the active controller. A voting circuit processes votes from the controllers and the active controller switch signal from the peripheral units to select the active controller. The signaling paths between the controllers used to convey votes and active controller information are duplicated. The signals on these signaling paths convey information by using oscillating signals of different frequencies.

Abstract: Controller triple modular redundancy is substantially achieved and reliability improved in a system having duplicate controllers that serve peripheral units. Both controllers detect suspected faults in itself and in the other controller. A peripheral unit that suspects a faulty active controller requests a switch of the active controller. A voting circuit processes votes from the controllers and the active controller switch signal from the peripheral units to select the active controller. The signaling paths between the controllers used to convey votes and active controller information are duplicated. The signals on these signaling paths convey information by using oscillating signals of different frequencies.

Abstract: A LAN switching system includes an Address Match Control line which can be set (activated) and is monitored by each port adapter card. If a port adapter card recognizes an address on the switch fabric, the adapter card copies the frame with the address and activates the Address match Control line. The set Address Match Control line causes the remaining port adapter cards to stop searching for a match. If the Address Match Control line is not set, the frame can be copied by all port adapters which are configured to do so.

Abstract: Method and apparatus for managing internal-node communications in a packet switching network by calculating optimal routes for packets and addressing subnodes within packet nodes using a specific message format. Internal communication facilities called intranode links connect multiple subnodes within nodes. Each subnode contains a switching mechanism and routes packet to other nodes, subnodes, or user applications using a specific message format. The message format allows specific subnodes anywhere in the network to the addressed by any other subnode, making communications more efficient and simplifying the management of internode links.