Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.

Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.

Abstract: An apparatus (46, 416, 470) is provided for sensing physical parameters. The apparatus (46, 416, 470) comprises a magnetic tunnel junction (MTJ) (32, 432), first and second electrodes (36, 38, 426, 434), a magnetic field source (MFS) (34, 445, 476) whose magnetic field (35) overlaps the MTJ (32, 432) and a moveable magnetic cladding element (33, 448, 478) whose proximity (43, 462, 479, 479?) to the MFS (34, 445, 476) varies in response to an input to the sensor. The MFS (34, 445, 476) is located between the cladding element (33, 448, 478) and the MTJ (32, 432). Motion (41, 41?, 41-1, 464, 477) of the cladding element (33, 448, 478) relative to the MFS (34, 445, 476) in response to sensor input causes the magnetic field (35) at the MTJ (32, 432) to change, thereby changing the electrical properties of the MTJ (32, 432). A one-to-one correspondence (54) between the sensor input and the electrical properties of the MTJ (32, 432) is obtained.

Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).

Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).

Abstract: Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.

Abstract: A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.

Abstract: A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Abstract: A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.

Abstract: A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.

Abstract: A stencil mask (12 or 12′) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.

Abstract: A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.

Abstract: A stencil mask (12 or 12′) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.