Patents by Inventor Kenneth Ho

Kenneth Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6864053
    Abstract: Detection of members of a conserved, dispersed gene family is used to ascertain levels of host cell genomic DNA in a sample.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: March 8, 2005
    Assignee: Cell Genesys
    Inventors: John M. Irving, Kenneth Ho, Michael Mok, Flavia Borellini
  • Publication number: 20050001958
    Abstract: A liquid crystal (LC) lightvalve comprising a twisted nematic LC layer whose molecules are aligned with pixel edges at the mirror backplane, thereby providing improved contrast and efficiency, and reduced visibility of post spacers in black state. The present invention is directed to an LC structure wherein the backplane is rubbed in a direction rectilinear with pixel edges. The LC layer is given the same twist rotation and birefringence as in the conventional TN lightvalve. Polarization control is maintained by illuminating the lightvalve with light whose polarization is rotated by the twist angle relative to the x,y, pixel axes, and by collecting the orthogonally polarized component of the reflected light. The lightvalve top glass is thus rubbed in a direction which is rotated by the twist angle from the horizontal or vertical direction at which the backplane is rubbed.
    Type: Application
    Filed: July 23, 2004
    Publication date: January 6, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth Ho, Minhua Lu, Alan Rosenbluth, Kei-Hsiung Yang
  • Patent number: 6696881
    Abstract: A method and apparatus for compensating for gate current through a first capacitor includes: a biasing circuit; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The biasing circuit ensures the bias voltage across the compensation capacitor is equal to the bias voltage across the first capacitor. In addition, the size of the second compensation transistor is chosen such that if, the ratio of the area of the compensation capacitor divided by the area of the first capacitor is area ratio “AR”, then, the ratio of the size of first compensation transistor divided by the size of second compensation transistor is also area ratio “AR”. As a result, according to the method and apparatus of the present invention, the gate current Ig through the first capacitor is equal to the current drained off through second compensation transistor.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: February 24, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Kenneth Ho
  • Publication number: 20020129036
    Abstract: A method and system for providing access to and management of multimedia files on a plurality of storage devices is described. The method can include: storing a plurality of multimedia files on at least one of the plurality of storage devices; providing access for a user to the plurality of multimedia files; means for encoding and decoding compressed multimedia files; and means for playing the plurality of multimedia files.
    Type: Application
    Filed: January 5, 2001
    Publication date: September 12, 2002
    Applicant: TeraOptix, Inc.
    Inventors: Kenneth Ho Yuen Lok, Kuan Yeh Cheang, Sebastian Lim Kim Seng
  • Patent number: 5469097
    Abstract: A translator circuit for providing symmetrical switching delays for use with a power line for a differential amplifier having a first signal line and a complementary second signal line, the translator circuit including: a first voltage clamp coupled to the first signal line and to the power line for limiting a voltage differential between the power line and the first signal line; and a second voltage clamp coupled to the power line and the second signal line for limiting a voltage differential between the power line and the second signal line. The translator circuit provides reduced sensitivity to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. The translator circuit also provides symmetrical tracking between the rise to rise and the fall to fall delays of an emitter coupled logic to complementary metal-oxide semiconductor translator circuit.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: November 21, 1995
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Kenneth Ho
  • Patent number: D428433
    Type: Grant
    Filed: April 21, 1999
    Date of Patent: July 18, 2000
    Assignee: Ying Leung International Ltd.
    Inventor: Yiu-Ming Kenneth Ho