Abstract: A spread spectrum generator module is configured to provide data for spreading frequency spectra of at least first and second lower bandwidth asynchronously clocked communication links. A packet scheduling module aggregates the two (or more) lower bandwidth links into a higher bandwidth link or interface. The frequency spectra of the lower bandwidth links are spread in accordance with the data for spreading the frequency spectra. A downstream disaggregation element filters high frequency noise resulting from the spreading of the spectra.

Abstract: A method of processing cells in a communication system includes obtaining a cell, causing it to be stored, determined if it is associated with a loss event, and if so, causing it to be tagged with a lost cell indicator. An apparatus for processing cells includes a cell processing module and a cell buffer interface that can interface with a cell buffer. The processing module is configured to obtain a cell, cause it to be stored through the buffer interface, determine if it is associated with a loss event, and if so, cause it to be tagged with a lost cell indicator. The lost cell indicator can preferably be a compressed lost cell indicator. The inventive tagging enhances computational efficiency compared to approaches that require moving a stored cell to make room for a complete dummy cell.

Abstract: A spread spectrum generator module is configured to provide data for spreading frequency spectra of at least first and second lower bandwidth asynchronously clocked communication links. A packet scheduling module aggregates the two (or more) lower bandwidth links into a higher bandwidth link or interface. The frequency spectra of the lower bandwidth links are spread in accordance with the data for spreading the frequency spectra. A downstream disaggregation element filters high frequency noise resulting from the spreading of the spectra.

Abstract: An apparatus for interfacing with a cell delay variation buffer and a re-assembly memory buffer includes a header and sequence number processing module that can interface with the cell delay variation buffer and a re-assembly processing module that can interface with the re-assembly memory buffer. The header and sequence number processing module causes payloads from the cells to be stored in annotated form in the cell delay variation buffer and then extracted. Payload information from the extracted annotated payload can be passed to the re-assembly processing module which causes it to be stored in the re-assembly memory buffer and extracted therefrom as needed. By splitting the cell delay variation and re-assembly buffer functions, less expensive commodity memory can be used for the cell delay variation buffer function.

Abstract: At least one cell in a communications system, from a network side, is caused to be stored into a cell buffer bulk memory. Responsive to detecting a predetermined fullness condition of a timeslot memory buffer, a predetermined number of bytes (corresponding to a fraction of the payload of the cell) are caused to be retrieved from the cell buffer bulk memory into the timeslot memory buffer. Responsive to a line-side data requirement, at least one of the predetermined number of bytes is caused to be retrieved from the timeslot memory buffer to a line side. By handling fractions of cells, the amount of dedicated high-speed memory required in prior-art techniques can be significantly reduced.

Abstract: At least one cell in a communications system, from a network side, is caused to be stored into a cell buffer bulk memory. Responsive to detecting a predetermined fullness condition of a timeslot memory buffer, a predetermined number of bytes (corresponding to a fraction of the payload of the cell) are caused to be retrieved from the cell buffer bulk memory into the timeslot memory buffer. Responsive to a line-side data requirement, at least one of the predetermined number of bytes is caused to be retrieved from the timeslot memory buffer to a line side. By handling fractions of cells, the amount of dedicated high-speed memory required in prior-art techniques can be significantly reduced.

Abstract: A method of processing cells in a communication system includes obtaining a cell, causing it to be stored, determined if it is associated with a loss event, and if so, causing it to be tagged with a lost cell indicator. An apparatus for processing cells includes a cell processing module and a cell buffer interface that can interface with a cell buffer. The processing module is configured to obtain a cell, cause it to be stored through the buffer interface, determine if it is associated with a loss event, and if so, cause it to be tagged with a lost cell indicator. The lost cell indicator can preferably be a compressed lost cell indicator. The inventive tagging enhances computational efficiency compared to approaches that require moving a stored cell to make room for a complete dummy cell.

Abstract: An apparatus for interfacing with a cell delay variation buffer and a re-assembly memory buffer includes a header and sequence number processing module that can interface with the cell delay variation buffer and a re-assembly processing module that can interface with the re-assembly memory buffer. The header and sequence number processing module causes payloads from the cells to be stored in annotated form in the cell delay variation buffer and then extracted. Payload information from the extracted annotated payload can be passed to the re-assembly processing module which causes it to be stored in the re-assembly memory buffer and extracted therefrom as needed. By splitting the cell delay variation and re-assembly buffer functions, less expensive commodity memory can be used for the cell delay variation buffer function.

Abstract: A method and apparatus are disclosed for ATM Adaptation Layer (AAL) staggered constant bit rate cell scheduling. Cells from a plurality of virtual circuits are scheduled. Each of the virtual circuits have a transmission characteristic and each of the plurality of virtual circuits are classified into one of a plurality of stagger groups based on similar transmission characteristics. For each frame synchronization, a cell is transmitted from a given virtual circuit until a predefined cell threshold is exceeded for the stagger group containing the given virtual circuit. A Cell Delay Variation of each of the virtual circuits will not exceed a given time interval. A scheduler can be allocated for each connection or for each period.