Abstract: In a first aspect, a first method is provided for controlling the flow of data between a first and second clock domain. The first method includes the steps of (1) selecting one of a plurality of ports included in a physical layer interface in the second clock domain to which to send data; and (2) transmitting data from a transmit buffer in the first clock domain to the selected port in the physical layer interface in the second clock domain. Numerous other aspects are provided.

Abstract: An ATM communications network includes a system processor having a device driver and a memory coupled to an adapter at an interface. Frames stored in the memory are transmitted to the network using a transmit ready queue residing in the adapter and defined by transmit control registers. The frames are linked together by descriptors and pointers to received ready lists maintained by the device driver. A transmit frame complete list is established in the system memory using the transmit control registers. An interrupt is generated by the adapter indicating when frame transmission is complete. Simultaneously, cells are received from the network and stored in system memory according to a free buffer list established by the device driver. A pointer is maintained by the device driver to the last entry of the receive free buffer list. The adapter maintains a pointer to the next buffer to be used from the receive free buffer list.

Abstract: The connection capability of a communication controller is extended. The communication controller includes a central control unit CCU, running a network control program NCP stored in a memory having a direct memory access facility through a DMA bus. The input/output bus of the communication controller and DMA bus are connected to line adapters, and channel adapters and a controller extension through a coupler which allows additional adapters to be connected to the controller. At initialization, a table is built into a coupler memory, which is then used in steady state mode for controlling the transmission of the messages to the additional users and the reception of the messages from the additional users, by improving the buffer unchaining and chaining processes into the NCP memory.

Abstract: A system and process are disclosed that allows the collection of events to be organized and ordered so that relationship between events and the events themselves can be identified as a state or series of states which describe and allow control of performance aspects of protocol activity. The architecture allows dynamic programming of multiple of devices for the purposes of coordination and correlation of events such that monitoring, performance analysis and control can be accomplished on a real-time basis for any speed network. The architecture facilitates feedback of the correlated events for the purposes of monitoring and controlling network activity.

Abstract: An Event Driven Interface (EDI) is disclosed for use as a subsystem of a monitoring and control system for a data communications network. The network communicates a serial stream of binary bits having a characteristic pattern. The system includes a control vector generator for generating a control vector C(i) which describes the characteristic pattern and an event vector analyzer for analyzing an event vector E(i) which represents a plurality of occurrences of the pattern on the network.

Abstract: The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48).The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter.