Patents by Inventor Kenneth J. Duda

Kenneth J. Duda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10644969
    Abstract: In general, the invention relates to a method and system for probing forwarding elements of network elements.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 5, 2020
    Assignee: Arista Networks, Inc.
    Inventors: Hugh W. Holbrook, Kenneth J. Duda
  • Patent number: 10644975
    Abstract: In general, the invention relates to a method and system for probing forwarding elements of network elements.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 5, 2020
    Assignee: Arista Networks, Inc.
    Inventors: Kenneth J. Duda, Hugh W. Holbrook
  • Publication number: 20190052556
    Abstract: In general, the invention relates to a method and system for probing forwarding elements of network elements.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 14, 2019
    Inventors: Kenneth J. Duda, Hugh W. Holbrook
  • Publication number: 20190052552
    Abstract: In general, the invention relates to a method and system for probing forwarding elements of network elements.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 14, 2019
    Inventors: Hugh W. Holbrook, Kenneth J. Duda
  • Patent number: 9306804
    Abstract: A method for performing an in-service software update in a MLAG domain. The method includes restarting the first switch using a second version of software, detecting by a second switch that the first switch is restarting and, in response to the detection, SSO. After restarting the first switch, prior to the first switch performing graceful reinsertion into the MLAG domain, setting all non-peer ports on the first switch to an error-disabled state and selecting a common MLAG protocol version supported by the first switch and the second switch and performing graceful reinsertion, which includes reestablishing a peering relationship between the first switch and the second switch using the common MLAG protocol, and after reestablishing the peering relationship, synchronizing a control plane state of the first switch with the control plane state of the second switch and setting all non-peer ports on the first switch to an active state.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 5, 2016
    Assignee: Arista Networks, Inc.
    Inventors: Kenneth J. Duda, Roger S. Liao, Nathan D. Arroyo
  • Patent number: 9030931
    Abstract: A method for accurately measuring, recording and reporting latency of an Ethernet switch is disclosed. Various packet queues in the switch are monitored at any given time and forwarding latency is calculated. Latency data from multiple switching elements in a network is collected to provide end-to-end forwarding latency of a system.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 12, 2015
    Assignee: Arista Networks, Inc.
    Inventors: Kenneth J. Duda, Anshul Sadana, Hugh W. Holbrook
  • Publication number: 20140307540
    Abstract: A method for performing an in-service software update in a MLAG domain. The method includes restarting the first switch using a second version of software, detecting by a second switch that the first switch is restarting and, in response to the detection, SSO. After restarting the first switch, prior to the first switch performing graceful reinsertion into the MLAG domain, setting all non-peer ports on the first switch to an error-disabled state and selecting a common MLAG protocol version supported by the first switch and the second switch and performing graceful reinsertion, which includes reestablishing a peering relationship between the first switch and the second switch using the common MLAG protocol, and after reestablishing the peering relationship, synchronizing a control plane state of the first switch with the control plane state of the second switch and setting all non-peer ports on the first switch to an active state.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: ARISTA NETWORKS, INC.
    Inventors: Kenneth J. Duda, Roger S. Liao, Nathan D. Arroyo
  • Publication number: 20120236723
    Abstract: A method for accurately measuring, recording and reporting latency of an Ethernet switch is disclosed. Various packet queues in the switch are monitored at any given time and forwarding latency is calculated. Latency data from multiple switching elements in a network is collected to provide end-to-end forwarding latency of a system.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 20, 2012
    Inventors: Kenneth J. Duda, Anshul Sadana, Hugh W. Holbrook
  • Patent number: 7921422
    Abstract: A scheduling mechanism that fairly allocates a resource to a number of schedulable elements, of which some are latency-sensitive, is disclosed. Each element's use of the resource is tracked by determining the element's virtual time. An active element is selected from the elements that are ready to use the resource by determining the element that has the smallest effective virtual time. The effective virtual time is the element's actual virtual time modified by a borrowed virtual time value. When an element has a short-term need for the resource, it can borrow the privilege to run by borrowing virtual time. As the element uses the resource, it consumes virtual time according to its weight. When the elements are scheduled for the resource, the ready element having the smallest virtual time is selected. The invention enforces long-term fairness to each element while allowing latency-sensitive elements to be preferably selected.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: April 5, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth J. Duda, David R. Cheriton
  • Publication number: 20090144538
    Abstract: A method for booting a computer operating system is provided. A boot loader is loaded from a first flash memory to a random access memory and executed. In one embodiment, the boot loader loads from a second flash memory to a random access memory an operating system file system image archive, installs the operating system file system image archive as a root file system, loads from the second flash memory multiple operating system patches stored separately from the base operating system file system image archive, and installs the multiple operating system patches over the root file system. In another embodiment, the boot loader loads and executes an initialization script that performs the operations instead of the boot loader.
    Type: Application
    Filed: November 5, 2008
    Publication date: June 4, 2009
    Inventors: Kenneth J. Duda, Edward R. Swierk
  • Publication number: 20090138692
    Abstract: A network switch device includes a switch chassis, a supervisor mounted in the switch chassis; and a line card mounted in the chassis. The line card has independently addressable line card hardware components, and a line card memory storing a software-readable description of the line card hardware components. The supervisor controller reads the software-readable description of the line card hardware components from the line card, and creates software drivers for the line card hardware components from the software-readable description of the line card hardware components.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 28, 2009
    Inventors: Kenneth J. Duda, Hugh W. Holbrook, Lorenz W. Redlefsen
  • Patent number: 7065762
    Abstract: The present invention includes a scheduling mechanism that fairly allocates a resource to a number of schedulable elements of which some are latency-sensitive. The invention tracks each element's use of the resource by determining the element's virtual time. An active element is selected from the elements that are ready to use the resource by determining the element that has the smallest effective virtual time. The effective virtual time is the element's actual virtual time modified by a borrowed virtual time value. When an element has a short-term need for the resource, it can borrow the privilege to run by borrowing virtual time. As the element uses the resource, it consumes virtual time according to its weight. When the elements are scheduled for the resource, the ready elements having the smallest virtual time is selected. The invention enforces long-term fairness to each element while allowing latency-sensitive elements to be preferably selected.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: June 20, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth J. Duda, David R. Cheriton
  • Patent number: 6628287
    Abstract: A set of mechanisms provides consistency, responsiveness, and integrity, to allow high-realism in a distributed network simulation environment. Consistency is achieved by executing the same computation with the same inputs on multiple machines. Responsiveness is achieved by executing the parts of the computation that affect the user's object earlier on the user's machine than on the server for the user's object. Integrity is achieved by executing all computations authoritatively on the server. The ability to run different parts of a shared computation at varying times on different machines is provided.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: September 30, 2003
    Assignee: There, Inc.
    Inventors: Kenneth J. Duda, William D. Harvey
  • Patent number: 5857091
    Abstract: A machine and method for allowing a simulated processor environment to interact with a simulated digital environment to simulate a processor-based system. Embodiments of the present invention contemplate that interaction between the processor environment and digital environment can be implemented by providing the processor environment with a list of "significant events" (e.g., reads and writes) that are pertinent to the digital environment. Embodiments of the present invention also contemplate that the processor environment and digital environment can be synchronized by allowing operations to occur on either the processor environment or the digital environment, but not on both simultaneously.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: January 5, 1999
    Assignee: Siemens Business Communication Systems, Inc.
    Inventors: Neufito L. Fernandes, Kenneth J. Duda, Alfred Platt