Abstract: A wideband RF tuner with blocker signal detector for detection of blocking signals and for fast recovery from noise limited region.

Abstract: A method of operating a radio frequency transceiver may include generating, by a transmit circuit of the transceiver, in-phase (I) and quadrature (Q) analog signals based on a digital calibration signal; mixing, by the transmit circuit, the I and Q analog signals with local oscillator (LO) and phase shifted LO signals to generate upconverted I and Q signals, the LO signal having a first frequency, and combining the upconverted I and Q signals to generate a combined signal; and converting, by a receive circuit of the transceiver, a signal based on the combined signal to a received digital signal using a sampling rate at a second frequency, the second frequency being less than the first frequency, wherein the converting downconverts frequency content in the combined signal.

Abstract: A wideband RF tuner with blocker signal detector for detection of blocking signals and for fast recovery from noise limited region.

Abstract: A method of operating a radio frequency transceiver may include generating, by a transmit circuit of the transceiver, in-phase (I) and quadrature (Q) analog signals based on a digital calibration signal; mixing, by the transmit circuit, the I and Q analog signals with local oscillator (LO) and phase shifted LO signals to generate upconverted I and Q signals, the LO signal having a first frequency, and combining the upconverted I and Q signals to generate a combined signal; and converting, by a receive circuit of the transceiver, a signal based on the combined signal to a received digital signal using a sampling rate at a second frequency, the second frequency being less than the first frequency, wherein the converting downconverts frequency content in the combined signal.

Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.

Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.

Abstract: A spread-spectrum receiver for time sharing a correlator for simultaneously receiving a plurality of parallel spread-spectrum signals. A combined multiplicity of symbols includes a multiplicity of symbols, simultaneously occurring during a symbol-time duration, from a plurality of spread-spectrum signals. A demultiplexer demultiplexes a sequence of the combined multiplicity of symbols into a plurality of symbol registers. Each of the symbol registers stores the chip-sequence signals corresponding to the combined multiplicity of symbols which were sent to the particular symbol register. A multiplexer selects a symbol register, other than the symbol register selected by the demultiplexer. The multiplicity of chip-sequence signals stored in the selected symbol register by the multiplexer are compared by a comparator with a multiplicity of replicas of the chip-sequence signals used to generate the spread-spectrum signals.

Abstract: A digital microelectronic replacement package includes at least one buffer die in combination with a programmable device or memory. The buffer die performs the functions of impedance-matching, delay-matching, and voltage-matching, while the programmable device or memory can be used to emulate the logic and/or storage functions of the original digital microelectronic circuit; the package of the invention can be used as a direct replacement for a digital microelectronic circuit without the requirement that the original circuit board be redesigned to accommodate modern voltage, impedance, and delay specifications associated with the programmable device or memory.