Patents by Inventor Kenneth J. Keyes, Jr.

Kenneth J. Keyes, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RF tuner with blocker detection and noise limited region recovery
    Patent number: 9859915
    Abstract: A wideband RF tuner with blocker signal detector for detection of blocking signals and for fast recovery from noise limited region.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 2, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Reza Alavi, Shobhit Agrawal, Kenneth J Keyes, Jr.
  • CONFIGURABLE QUAD BYTE FRAMER
    Publication number: 20150016471
    Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 15, 2015
    Applicant: Analog Devices, Inc.
    Inventors: Kenneth J. Keyes, JR., Syed Haider
  • JESD TEST SEQUENCER GENERATOR
    Publication number: 20150016272
    Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 15, 2015
    Applicant: ALALOG DEVICES, INC.
    Inventor: Kenneth J. Keyes, JR.
  • Digital microelectronic circuit package using buffer dies and programmable device or memory dies
    Patent number: 5781791
    Abstract: A digital microelectronic replacement package includes at least one buffer die in combination with a programmable device or memory. The buffer die performs the functions of impedance-matching, delay-matching, and voltage-matching, while the programmable device or memory can be used to emulate the logic and/or storage functions of the original digital microelectronic circuit; the package of the invention can be used as a direct replacement for a digital microelectronic circuit without the requirement that the original circuit board be redesigned to accommodate modern voltage, impedance, and delay specifications associated with the programmable device or memory.
    Type: Grant
    Filed: April 16, 1996
    Date of Patent: July 14, 1998
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Michael A. Dukes, Kenneth J. Keyes, Jr., Gerald T. Michael