Patents by Inventor Kenneth J. Keys, Jr.

Kenneth J. Keys, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable quad byte framer
    Patent number: 9288286
    Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: March 15, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Kenneth J. Keys, Jr., Syed Haider
  • JESD test sequencer generator
    Patent number: 9143423
    Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: September 22, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventor: Kenneth J. Keys, Jr.