Patents by Inventor Kenneth J. Maggio
Kenneth J. Maggio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411424Abstract: This disclosure relates to a system that includes a boost circuit comprising a boost capacitor. The boost circuit is configured to provide a boost voltage at a first terminal of the boost capacitor by increasing the boost voltage at the first terminal to exceed a target voltage for a given charge cycle. A boost switch is configured to supply the boost voltage from the first terminal to a charge node for turning on a transistor, which is coupled to the charge node, based on a boost signal during the given charge cycle. A pull-down circuit is configured to control discharge of the charge node to a clamp voltage that is sufficient to turn off the transistor for the given charge cycle and to facilitate charging of the charge node in a next charge cycle.Type: GrantFiled: April 24, 2020Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Huawen Jin, Kenneth J. Maggio, Thomas James Jung, Jr.
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Publication number: 20200403434Abstract: This disclosure relates to a system that includes a boost circuit comprising a boost capacitor. The boost circuit is configured to provide a boost voltage at a first terminal of the boost capacitor by increasing the boost voltage at the first terminal to exceed a target voltage for a given charge cycle. A boost switch is configured to supply the boost voltage from the first terminal to a charge node for turning on a transistor, which is coupled to the charge node, based on a boost signal during the given charge cycle. A pull-down circuit is configured to control discharge of the charge node to a clamp voltage that is sufficient to turn off the transistor for the given charge cycle and to facilitate charging of the charge node in a next charge cycle.Type: ApplicationFiled: April 24, 2020Publication date: December 24, 2020Inventors: HUAWEN JIN, KENNETH J. MAGGIO, THOMAS JAMES JUNG, Jr.
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Patent number: 10784849Abstract: An energy storage element control circuit includes a charge transistor having a first node adapted to be coupled to an output node of the energy storage element control circuit and a second node adapted to be coupled to a terminal of an energy storage element. The energy storage control circuit also includes a boot capacitor having a first node and a second node. The energy storage element further includes a comparator that includes a first input node coupled to the first node of the charge transistor and a second input node adapted to be coupled to the terminal of the energy storage element. The comparator also includes an output node.Type: GrantFiled: August 29, 2019Date of Patent: September 22, 2020Assignee: Texas Instruments IncorporatedInventors: Bradford Lawrence Hunter, Kenneth J. Maggio, Christopher Lee Betty
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Publication number: 20200280307Abstract: An energy storage element control circuit includes a charge transistor having a first node adapted to be coupled to an output node of the energy storage element control circuit and a second node adapted to be coupled to a terminal of an energy storage element. The energy storage control circuit also includes a boot capacitor having a first node and a second node. The energy storage element further includes a comparator that includes a first input node coupled to the first node of the charge transistor and a second input node adapted to be coupled to the terminal of the energy storage element. The comparator also includes an output node.Type: ApplicationFiled: August 29, 2019Publication date: September 3, 2020Inventors: BRADFORD LAWRENCE HUNTER, KENNETH J. MAGGIO, CHRISTOPHER LEE BETTY
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Publication number: 20180323361Abstract: A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.Type: ApplicationFiled: July 10, 2018Publication date: November 8, 2018Inventors: Henry L. Edwards, Kenneth J. Maggio, Steven Kummerl, Sreenivasan K. Koduri
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Patent number: 9818795Abstract: In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.Type: GrantFiled: September 2, 2016Date of Patent: November 14, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey R. Debord, Henry Litzmann Edwards, Kenneth J. Maggio
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Publication number: 20160372516Abstract: In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Jeffrey R. Debord, Henry Litzmann Edwards, Kenneth J. Maggio
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Patent number: 9437652Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.Type: GrantFiled: May 30, 2014Date of Patent: September 6, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey R. Debord, Henry Litzmann Edwards, Kenneth J. Maggio
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Publication number: 20150349023Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Inventors: Jeffrey R. Debord, Henry Litzmann Edwards, Kenneth J. Maggio
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Patent number: 9088158Abstract: One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.Type: GrantFiled: December 5, 2013Date of Patent: July 21, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kenneth J. Maggio, Umar Jameer Lyles, John H. Carpenter, Jr., J. Randall Cooper, Vinod Mukundagiri
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Publication number: 20140160600Abstract: One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.Type: ApplicationFiled: December 5, 2013Publication date: June 12, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: KENNETH J. MAGGIO, Umar Jameer Lyles, John H. Carpenter, JR., J. Randall Cooper, Vinod Mukundagiri
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Patent number: 8155256Abstract: A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.Type: GrantFiled: October 2, 2001Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Kenneth J. Maggio, Dirk D. Leipold
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Patent number: 7667511Abstract: Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.Type: GrantFiled: August 2, 2005Date of Patent: February 23, 2010Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Dirk Leipold, Kenneth J. Maggio
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Publication number: 20090196384Abstract: A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).Type: ApplicationFiled: December 12, 2008Publication date: August 6, 2009Inventors: Robert B. Staszewski, Khurram Muhammad, Kenneth J. Maggio, Dirk Leipold
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Patent number: 7519135Abstract: A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).Type: GrantFiled: July 8, 2002Date of Patent: April 14, 2009Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Khurram Muhammad, Kenneth J. Maggio, Dirk Leipold
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Patent number: 7079826Abstract: A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding half-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform.Type: GrantFiled: March 15, 2002Date of Patent: July 18, 2006Assignee: Texas Instruments IncorporatedInventors: Khurram Muhammad, Dirk L. Leipold, Feng Chen, Kenneth J. Maggio
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Patent number: 7003276Abstract: A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.Type: GrantFiled: April 25, 2002Date of Patent: February 21, 2006Assignee: Texas Instruments IncorporatedInventors: Khurram Muhammad, Dirk Leipold, Kenneth J. Maggio
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Patent number: 6924681Abstract: Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.Type: GrantFiled: May 22, 2002Date of Patent: August 2, 2005Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Dirk Leipold, Kenneth J. Maggio
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Patent number: 6851493Abstract: A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, ?. During frequency/phase acquisition, a larger loop gain constant, ?1 is used such that the resulting phase error is within limits. After the frequency/phase gets acquired, the developed phase error, which is a rough indication of the frequency offset is in a steady-state condition. While transitioning into the tracking mode, the DC offset is added to the DCO tuning signal preferably the DC offset is added to the phase error signal and the loop constant is reduced from ?1 to ?2. This scheme provides for hitless operation, while requiring a low dynamic range of the phase detector (101).Type: GrantFiled: December 1, 2000Date of Patent: February 8, 2005Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Kenneth J. Maggio
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Publication number: 20030050027Abstract: A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding half-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform.Type: ApplicationFiled: March 15, 2002Publication date: March 13, 2003Inventors: Khurram Muhammad, Dirk Leipold, Feng Chen, Kenneth J. Maggio