Patents by Inventor Kenneth J. Mobley
Kenneth J. Mobley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7799598Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: GrantFiled: March 14, 2008Date of Patent: September 21, 2010Assignee: ZettaCore, Inc.Inventors: Werner G. Kuhr, Ritu Shrivastava, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske
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Patent number: 7737433Abstract: The electronic properties of molecular junctions of the general type carbon/molecule/TiO2/Au as examples of “molecular heterojunctions” consisting of a molecular monolayer and a semiconducting oxide. Junctions containing fluorene bonded to pyrolyzed photoresist film (PPF) were compared to those containing Al2O3 instead of fluorene, and those with only the TiO2 layer. The responses to voltage sweep and pulse stimulation were strongly dependent on junction composition and temperature. A transient current response lasting a few milliseconds results from injection and trapping of electrons in the TiO2 layer, and occurred in all three junction types studied. Conduction in PPF/TiO2/Au junctions is consistent with space charge limited conduction at low voltage, then a sharp increase in current once the space charge fills all the traps. With fluorene present, there is a slower, persistent change in junction conductance which may be removed by a reverse polarity pulse.Type: GrantFiled: September 28, 2006Date of Patent: June 15, 2010Assignees: The Ohio State University Research Foundation, Zettacore, Inc.Inventors: Richard L. McCreery, Kenneth J. Mobley, Jing Wu
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Patent number: 7688662Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.Type: GrantFiled: November 18, 2008Date of Patent: March 30, 2010Inventor: Kenneth J. Mobley
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Publication number: 20090122619Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.Type: ApplicationFiled: May 6, 2008Publication date: May 14, 2009Applicant: Purple Mountain Server LLCInventors: Ronald H. Sartore, Kenneth J. Mobley, Donald G. Carrigan, Oscar Frederick Jones, JR.
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Patent number: 7533231Abstract: A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A number of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, before application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.Type: GrantFiled: October 13, 2004Date of Patent: May 12, 2009Inventors: Kenneth J. Mobley, Michael T. Peters, Michael Schuette
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Publication number: 20090073794Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.Type: ApplicationFiled: November 18, 2008Publication date: March 19, 2009Applicant: PURPLE MOUNTAIN SERVER LLCInventor: Kenneth J. Mobley
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Patent number: 7453752Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.Type: GrantFiled: September 27, 2005Date of Patent: November 18, 2008Assignee: Purple Mountain Server LLCInventor: Kenneth J. Mobley
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Publication number: 20080219041Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: ApplicationFiled: March 14, 2008Publication date: September 11, 2008Inventors: Werner G. Kuhr, Ritu Shrivastava, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske
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Patent number: 7370140Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.Type: GrantFiled: September 24, 2001Date of Patent: May 6, 2008Assignee: Purple Mountain Server LLCInventors: Ronald H. Sartore, Kenneth J. Mobley, Donald G. Carrigan, Oscar Frederick Jones, Jr.
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Patent number: 7358113Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: GrantFiled: April 29, 2005Date of Patent: April 15, 2008Assignee: Zettacore, Inc.Inventors: Ritu Shrivastava, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske
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Patent number: 7085186Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.Type: GrantFiled: April 5, 2001Date of Patent: August 1, 2006Assignee: Purple Mountain Server LLCInventor: Kenneth J. Mobley
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Patent number: 6813679Abstract: An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.Type: GrantFiled: June 20, 2002Date of Patent: November 2, 2004Assignee: Purple Mountain Server LLCInventors: Kenneth J. Mobley, Michael T. Peters, Michael Schuette
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Publication number: 20030236958Abstract: An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.Type: ApplicationFiled: June 20, 2002Publication date: December 25, 2003Inventors: Kenneth J. Mobley, Michael T. Peters, Michael Schuette
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Patent number: 6538928Abstract: A memory architecture uses shared sense amplifiers (18-23) and a centralized cache (26-29) that contains M bits. The memory architecture also includes a global bus (31) connecting the sense amplifiers and the centralized cache. The global bus includes n bits, and n<M bits are transferred in M/n cycles to the centralized cache.Type: GrantFiled: October 11, 2000Date of Patent: March 25, 2003Assignee: Enhanced Memory Systems Inc.Inventor: Kenneth J. Mobley
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Patent number: 6501698Abstract: A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.Type: GrantFiled: November 1, 2000Date of Patent: December 31, 2002Assignee: Enhanced Memory Systems, Inc.Inventor: Kenneth J. Mobley
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Publication number: 20020147885Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i≠j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.Type: ApplicationFiled: April 5, 2001Publication date: October 10, 2002Inventor: Kenneth J. Mobley
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Publication number: 20020056020Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.Type: ApplicationFiled: September 24, 2001Publication date: May 9, 2002Inventors: Ronald H. Sartore, Kenneth J. Mobley, Donald G. Carrigan, Oscar Frederick Jones
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Patent number: 6347357Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.Type: GrantFiled: October 30, 1998Date of Patent: February 12, 2002Assignee: Enhanced Memory Systems, Inc.Inventors: Ronald H. Sartore, Kenneth J. Mobley, Donald G. Carrigan, Oscar Frederick Jones
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Patent number: 6330636Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device incorporating a static random access memory (“SRAM”) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page “hit” latency, faster page “miss” latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read “hit”.Type: GrantFiled: January 29, 1999Date of Patent: December 11, 2001Assignee: Enhanced Memory Systems, Inc.Inventors: David W. Bondurant, Michael Peters, Kenneth J. Mobley
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Patent number: 6289413Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data.Type: GrantFiled: October 15, 1999Date of Patent: September 11, 2001Assignee: International Business Machines Corp.Inventors: Jim L. Rogers, Steven W. Tomashot, David W. Bondurant, Oscar Frederick Jones, Jr., Kenneth J. Mobley