Patents by Inventor Kenneth J. Newton

Kenneth J. Newton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process flow for dual damescene interconnect structures
    Patent number: 6872665
    Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Francis G. Celii, Guoqiang Xing, Andrew McKerrow, Andrew Ralston, Zhicheng Tang, Kenneth J. Newton, Robert Kraft, Jeff West
  • Pre-pattern surface modification of low-k dielectrics
    Patent number: 6861348
    Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
  • In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
    Patent number: 6797633
    Abstract: After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: September 28, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Ping Jiang, Robert Kraft, Kenneth J. Newton, Daty M. Rogers
  • Method of forming dual-damascene structure
    Patent number: 6774031
    Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: August 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Abbas Ali, Kenneth J. Newton
  • Method of forming dual-damascene structure
    Publication number: 20040121581
    Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.
    Type: Application
    Filed: December 8, 2003
    Publication date: June 24, 2004
    Inventors: Abbas Ali, Kenneth J. Newton
  • Pre-pattern surface modification for low-k dielectrics using A H2 plasma
    Patent number: 6720247
    Abstract: A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: April 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
  • Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics
    Patent number: 6455411
    Abstract: A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: September 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Ping Jiang, Francis G. Celii, Kenneth J. Newton, Hiromi Sakima
  • Pre-pattern surface modification for low-k dielectrics using A H2 plasma
    Publication number: 20020111017
    Abstract: A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
    Type: Application
    Filed: October 25, 2001
    Publication date: August 15, 2002
    Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
  • Pre-pattern surface modification for low-k dielectrics
    Publication number: 20020111037
    Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
    Type: Application
    Filed: October 18, 2001
    Publication date: August 15, 2002
    Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
  • In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
    Publication number: 20020081855
    Abstract: After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.
    Type: Application
    Filed: September 28, 2001
    Publication date: June 27, 2002
    Inventors: Ping Jiang, Robert Kraft, Kenneth J. Newton, Daty M. Rogers
  • Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics
    Publication number: 20020031906
    Abstract: A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 14, 2002
    Inventors: Ping Jiang, Francis G. Celii, Kenneth J. Newton, Hiromi Sakima