Patents by Inventor Kenneth J. Polasko

Kenneth J. Polasko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5010018
    Abstract: A method for fabricating Schottky photodiodes includes the steps of: forming a base electrode on the principal substrate surface; depositing a layer of N+ amorphous silicon on the base electrode; depositing a layer of intrinsic silicon on the N+ amorphous silicon layer; depositing a Schottky contact on the intrinsic silicon layer; and selectively patterning the Schottky contact and the two silicon layers with the same photoresist mask to form a Schottky photodiode island.
    Type: Grant
    Filed: September 24, 1990
    Date of Patent: April 23, 1991
    Assignee: General Electric Company
    Inventors: Kenneth J. Polasko, Ivan L. Wemple
  • Patent number: 4982246
    Abstract: A Schottky photodiode formed by the method including the steps of: forming a base electrode on the principal substrate surface; depositing a layer of N+ amorphous silicon on the base electrode; depositing a layer of intrinsic silicon on the N+ amorphous silicon layer; depositing a Schottky contact on the intrinsic silicon layer; and selectively patterning the Schottky contact and the two silicon layers with the same photoresist mask to form a Schottky photodiode island.
    Type: Grant
    Filed: June 21, 1989
    Date of Patent: January 1, 1991
    Assignee: General Electric Company
    Inventors: Kenneth J. Polasko, Ivan L. Wemple
  • Patent number: 4895780
    Abstract: In order to solve the problem of the proximity effects which occurs in the fabrication of integrated circuit devices, a facile method is provided for automatically creating a new pattern in which variably spaced windage correction is applied over the mask. This permits the utilization of conventional design fabrication rules and systems without the concomitant problem of producing small feature sizes in isolated structures. The method produces highly desirable chip masks and is readily implemented on commercially available CAD systems presently being employed for the production of circuit masks. The method is automatic and extremely easily implemented.
    Type: Grant
    Filed: October 25, 1988
    Date of Patent: January 23, 1990
    Assignee: General Electric Company
    Inventors: Yoav Nissan-Cohen, Paul A. Frank, Joseph M. Pimbley, Dale M. Brown, Ernest W. Balch, Kenneth J. Polasko