Patents by Inventor Kenneth James Eldredge

Kenneth James Eldredge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods involving managing a problematic memory cell
    Patent number: 9378847
    Abstract: Subject matter described pertains to managing problematic memory cells in a memory array.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 28, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kenneth James Eldredge, Larry Joseph Koudele
  • SYSTEMS AND METHODS INVOLVING MANAGING A PROBLEMATIC MEMORY CELL
    Publication number: 20150380108
    Abstract: Subject matter described pertains to managing problematic memory cells in a memory array.
    Type: Application
    Filed: September 2, 2015
    Publication date: December 31, 2015
    Inventors: Kenneth James Eldredge, Larry Joseph Koudele
  • Systems and methods involving managing a problematic memory cell
    Patent number: 9128869
    Abstract: Methods and apparatus are provided for identifying which symbol within a codeword corresponds to an information state read from a problematic memory cell. A method can include applying a programming signal to a memory cell, and determining whether the programming signal programs the memory cell approximately within an operational range of a physical property of the memory cell. The method can include identifying which symbol within a codeword corresponds to an information state read from the memory cell, if the memory cell was not programmed approximately within the operational range of the physical property. Identifying the symbol can be done with a flag in the codeword.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth James Eldredge, Larry Joseph Koudele
  • SYSTEMS AND METHODS INVOLVING MANAGING A PROBLEMATIC MEMORY CELL
    Publication number: 20130086453
    Abstract: Subject matter described pertains to managing problematic memory cells in a memory array.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Kenneth James Eldredge, Larry Joseph Koudele
  • Micromover configured to move a magnetic storage medium in perpendicular directions in a plane
    Patent number: 7038878
    Abstract: A storage device comprising a magnetic storage medium mounted in a first plane, a read and write mechanism mounted in a second plane that is parallel to the first plane and configured to write information to the magnetic storage medium, and a micromover configured to move the magnetic storage medium in a first direction parallel to the first plane and configured to move the magnetic storage medium in a second direction parallel to the first plane and perpendicular to the first direction.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: May 2, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lung T. Tran, Andrew Van Brocklin, Kenneth James Eldredge
  • Storage structure with cleaved layer
    Patent number: 6967149
    Abstract: Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: November 22, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Neal W. Meyer, Andrew L. Van Brocklin, Peter Fricke, Warren Jackson, Kenneth James Eldredge
  • Memory device
    Patent number: 6873543
    Abstract: Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kenneth Kay Smith, Andrew VanBrocklin, Peter Fricke, Frederick A. Perner, Kenneth James Eldredge
  • Memory system having control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells
    Patent number: 6839275
    Abstract: Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: January 4, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andrew L Van Brocklin, Kenneth Smith, Kenneth James Eldredge, Peter James Fricke
  • MEMORY SYSTEM
    Publication number: 20040246774
    Abstract: Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Inventors: Andrew L. Van Brocklin, Kenneth Smith, Kenneth James Eldredge, Peter James Fricke
  • Memory device
    Publication number: 20040240255
    Abstract: Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventors: Kenneth Kay Smith, Andrew Van Brocklin, Peter Fricke, Frederick A. Perner, Kenneth James Eldredge