Abstract: Embodiments of the present disclosure describe fabric covers, such as those used for air conditioning units, having a first air permeable panel for covering a horizontal top panel of an air conditioner unit; a second air permeable panel extending downward from the first air permeable panel for covering vertical side panels of the air conditioner unit; and an adjustable fastener provided in a bottom portion of the second air permeable panel for securing the cover to a base of the air conditioner unit.

Abstract: Embodiments of the present disclosure describe fabric covers, such as those used for air conditioning units, having a first air permeable panel for covering a horizontal top panel of an air conditioner unit; a second air permeable panel extending downward from the first air permeable panel for covering vertical side panels of the air conditioner unit; and an adjustable fastener provided in a bottom portion of the second air permeable panel for securing the cover to a base of the air conditioner unit.

Abstract: Embodiments of the present disclosure describe covers for air conditioner units comprising a first air permeable panel for covering a horizontal top panel of an air conditioner unit; a second air permeable panel extending downward from the first air permeable panel for covering vertical side panels of the air conditioner unit; and an adjustable fastener provided in a bottom portion of the second air permeable panel for securing the cover to a base of the air conditioner unit.

Abstract: A system includes cascaded content addressable memory (CAM) chips connected to a common bus. Each CAM chip includes a CAM array, a self-timed signal generator and hit propagation and match address transfer circuits. Each CAM array including an array of core cells provides, through its encoder, hit and match address signals resulting from a search operation in response to a clock signal. Each match address transfer circuit transfers the match address signal to the common bus, in response to a self-timed signal, the hit signal and a propagation-in hit signal provided from an upstream CAM chip, so that more than one CAM chip is prevented from providing the match address signal to the common bus simultaneously. Each hit propagation circuit provides a propagation-out hit signal to a downstream CAM chip, in response to the self-timed signal, the hit signal and the propagation-in hit signal from the upstream CAM chip, so that a hit signal is propagated from an upstream CAM chip to a downstream CAM chip.

Abstract: A system includes a plurality of content addressable memory (CAM) chips which are cascaded and connected to a common bus. Each of the CAM chips provides search results (hit, match address and multiple match). A hit signal and a multiple match signal are propagated from chip to chip. A system hit result is given from the furthest down stream CAM chip. The match address result of the system is given from the common bus, where on-chip self-timed signals guarantee that there is no driving contention on the bus. An example of the CAM chip includes an extra row including a model match line and modified core cells to provide a model miss signal. The self-timed signal is provided in response to the model match line. In another example of the CAM chip, each word is divided into two halves. The match lines of the two halves of the word are coupled by a NAND circuit, the output of which is coupled to an encoder of the chip. The CAM chip includes an extra row including a chain of model match lines.

Abstract: A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits which are connected to a commonly shared bus. Each CAM array provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. Hit, match address and multiple match signals are provided from the CAM arrays to the logic circuits which are associated with the CAM arrays. The hit signals provided from the CAM arrays are propagated from upstream to downstream logic circuits in response to a self-timed signal which is delayed in time from the clock signal. The logic circuits prevent more than one match address signal provided from the CAM array from being transferred simultaneously to the commonly shared bus. The multiple match signals provided from the CAM arrays are propagated from upstream to downstream logic circuits.

Abstract: A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits. The logic circuits are connected to a commonly shared bus. Each of the logic circuits is associated with the respective CAM array. Each of the CAM arrays provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. The hit signals provided from the CAM arrays to the respective logic circuits. Each logic circuit provides an OR logic output signal from a hit signal input from an upstream logic circuit and the hit signal provided by the CAM array associated with that logic circuit, in response to a self-timed signal which is delayed in time from the clock signal. The OR logic output signal provided by the logic circuit is provided to a downstream logic circuit. Thus, the furthest downstream logic circuit provides a hit result of the system in a search operation.

Abstract: A large-capacity CAM (content addressable memory) is disclosed. RAM core cells are used to store the CAM data. The comparison function is not performed in the core cells, but rather in comparators which are placed adjacent to a plurality of core cells, in such a way that the plurality of core cells shares access to a single comparator. Access to the comparator is shared by a time-division multiplexed means, requiring a plurality of serialized operations. These operations are self-timed and transparent to the user, because they occur in a single cycle of the externally-supplied clock.

Abstract: A large-capacity CAM (content addressable memory) is disclosed. RAM core cells are used to store the CAM data. The comparison function is not performed in the core cells, but rather in comparators which are placed adjacent to a plurality of core cells, in such a way that the plurality of core cells shares access to a single comparator. Access to the comparator is shared by a time-division multiplexed means, requiring a plurality of serialized operations. These operations are self-timed and transparent to the user, because they occur in a single cycle of the externally-supplied clock.

Abstract: A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global data signal. This signal interacts with two major control signals to self-time the memory. The number of major control signals is such that all possible memory states are uniquely represented, but the memory cannot power-up in an invalid or unrecoverable state. Three model timing paths are used to match the delay of the self-timing loop with that of the actual operation: one each for READ, WRITE and SEARCH.

Abstract: The implementation of two-dimensional decoding, necessary to achieve a reasonable array aspect ratio for a large content addressable memory, is achieved by having multiple match lines per physical row, these match lines being physically routed on top of the array core cell in an upper metal layer. To limit power dissipation in the resulting large-capacity content addressable memory, the match function is implemented by two or more NAND chains per word. Means for achieving the precharging and evaluation of these chains, and for implementing dummy chains for the provision of timing information, are also disclosed.

Abstract: A large-capacity CAM (content addressable memory) is disclosed. RAM core cells are used to store the CAM data. The comparison function is not performed in the core cells, but rather in comparators which are placed adjacent to a plurality of core cells, in such a way that the plurality of core cells shares access to a single comparator. Access to the comparator is shared by a time-division multiplexed means, requiring a plurality of serialized operations. These operations are self-timed and transparent to the user, because they occur in a single cycle of the externally-supplied clock.