Abstract: An eUSB repeater is described for passing repeating mode packets between a differential bus and a single-ended bus. An eUSB transceiver is coupled to a single ended bus, a USB transceiver is coupled to a differential bus, and repeater logic is coupled to and between the eUSB transceiver and the USB transceiver. A first enable control circuit receives a digital state transition from the differential data bus and generates an enable signal to an analog single-ended transmitter of the eUSB transceiver. A second enable control circuit receives a digital state transition from the single-ended data bus and generates an enable signal to an analog differential transmitter of the USB transceiver.

Abstract: Embodiments of a method and a device of lockup detection for an eUSB repeater are described. In an embodiment, the method involves detecting received data at an analog receiver on a first side of the eUSB repeater, detecting an enable signal for an analog transmitter on a second side of the eUSB repeater, detecting an idle condition of the analog receiver on the first side of the eUSB repeater after detecting the enable signal, setting a timer, determining that the timer has elapsed, and resetting the eUSB repeater after the timer has elapsed while an idle condition is detected on the first side and the enable signal is detected on the second side of the eUSB repeater.

Abstract: One example discloses a communications device, including: an interface port, configured to couple the communications device to another device; a transmitter configured to transmit signals on the interface port; a receiver configured to receive signals on the interface port; and a switch configured to short the interface port to a reference potential after the transmitter transmits signals on the interface port.

Abstract: A bus system, including a clock line, a first data line, and a second data line. The bus system further includes an initiator connected to a first end of the clock line, the first data line, and the second data line. The initiator sends a start indication on the clock line and the first data line, sends command bits followed by address bits on the first data line, and sends a stop indication on the clock line and the first data line. The bus system also includes a target connected to a second end of the clock line, the first data line, and the second data line. The target sends target acknowledge information followed by target interrupt information on the second line while the command bits and address bits are sent.

Abstract: A detector circuit is described for start signaling in an eUSB repeater. In an example, a circuit includes an analog differential transceiver configured to receive a differential data signal from a differential data bus and configured to drive a differential data signal to the differential data bus, an analog single-ended transceiver configured to receive a single-ended data signal from a single-ended data bus and configured to drive a single-ended data signal to the single-ended data bus, repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the differential data bus and the single-ended data bus, the repeater logic having an active state and a low power state, and a detection circuit coupled to the analog single-ended transceiver to detect a start signal on the single-ended data bus and to generate a wake signal to the repeater logic upon detecting the start signal.

Abstract: An eUSB repeater is described for passing repeating mode packets between a differential bus and a single-ended bus. An eUSB transceiver is coupled to a single ended bus, a USB transceiver is coupled to a differential bus, and repeater logic is coupled to and between the eUSB transceiver and the USB transceiver. A first enable control circuit receives a digital state transition from the differential data bus and generates an enable signal to an analog single-ended transmitter of the eUSB transceiver. A second enable control circuit receives a digital state transition from the single-ended data bus and generates an enable signal to an analog differential transmitter of the USB transceiver.

Abstract: A detector circuit of an eUSB repeater is coupled to a USB bus to detect a wake signal from a device through the USB bus and to send a forced resume signal to the device in response thereto. Repeater logic of the eUSB repeater repeats the received wake signal to the host. The host has a suspend state and an active state. The detector circuit detects the host resume signal from the host in the active state and stops sending the forced resume signal to the device in response thereto.

Abstract: A detector circuit is described for start signaling in an eUSB repeater. In an example, a circuit includes an analog differential transceiver configured to receive a differential data signal from a differential data bus and configured to drive a differential data signal to the differential data bus, an analog single-ended transceiver configured to receive a single-ended data signal from a single-ended data bus and configured to drive a single-ended data signal to the single-ended data bus, repeater logic coupled to the analog differential transceiver and the analog single-ended transceiver to repeat data signals between the differential data bus and the single-ended data bus, the repeater logic having an active state and a low power state, and a detection circuit coupled to the analog single-ended transceiver to detect a start signal on the single-ended data bus and to generate a wake signal to the repeater logic upon detecting the start signal.

Abstract: Embodiments of a method and a device of lockup detection for an eUSB repeater are described. In an embodiment, the method involves detecting received data at an analog receiver on a first side of the eUSB repeater, detecting an enable signal for an analog transmitter on a second side of the eUSB repeater, detecting an idle condition of the analog receiver on the first side of the eUSB repeater after detecting the enable signal, setting a timer, determining that the timer has elapsed, and resetting the eUSB repeater after the timer has elapsed while an idle condition is detected on the first side and the enable signal is detected on the second side of the eUSB repeater.

Abstract: An apparatus for determining a disconnection of a device from a bus, the apparatus comprising: a detection unit configured to periodically poll the bus, to detect an occurrence of an indicator of disconnection; and a handling unit configured to, in response to detecting the occurrence of an indicator of disconnection a predetermined number of times within a predetermined interval, make a determination that the device is disconnected from the bus. A method for determining a disconnection of a device from a bus is also presented.

Abstract: One example discloses a communications device, including: an interface port, configured to couple the communications device to another device; a transmitter configured to transmit signals on the interface port; a receiver configured to receive signals on the interface port; and a switch configured to short the interface port to a reference potential after the transmitter transmits signals on the interface port.

Abstract: Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

Abstract: Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

Abstract: Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Abstract: A universal serial bus (USB) circuit includes a USB interface configured to transmit and receive power and data, a random number generator circuit configured to generate a random number, and a controller configured to receive the random number and to select a dual role port (DRP) duty cycle and to select a DRP duration based upon the random number, wherein the DRP duty cycle time and DRP duration are used when connecting a USB type-C DRP device to another USB type-C DRP device.

Abstract: A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.

Abstract: Disclosed is a method of controlling a USB Power Delivery System including determining whether at least a predetermined length of initial bits of a message is received, turning on a clock when the predetermined length is received, determining whether the message has stopped, starting a counter when the message has stopped, determining whether a count value of the counter has reached a predetermined value, and turning off the clock when the predetermined count value has been reached.

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Abstract: Disclosed is a method of controlling a USB Power Delivery System including determining whether at least a predetermined length of initial bits of a message is received, turning on a clock when the predetermined length is received, determining whether the message has stopped, starting a counter when the message has stopped, determining whether a count value of the counter has reached a predetermined value, and turning off the clock when the predetermined count value has been reached.