Abstract: A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

Abstract: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

Abstract: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

Abstract: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

Abstract: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

Abstract: In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.

Abstract: A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

Abstract: An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.