Patents by Inventor Kenneth Kin Wai Wong

Kenneth Kin Wai Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital hold in a phase-locked loop
    Patent number: 8532243
    Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Srisai R. Seethamraju, Jerrell P. Hein, Kenneth Kin Wai Wong, Qicheng Yu
  • DIGITAL HOLD IN A PHASE-LOCKED LOOP
    Publication number: 20080191762
    Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 14, 2008
    Inventors: Srisai R. Seethamraju, Jerrell P. Hein, Kenneth Kin Wai Wong, Qicheng Yu