Patents by Inventor Kenneth Koch
Kenneth Koch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250145496Abstract: A method of operating a filtration system including a hybrid filter assembly is provided. The method includes the steps of providing a pump that is in fluid communication with a pool or a spa, providing a hybrid filter assembly including a filtration module, providing a chemical cleaning system including a container configured to retain a chemical cleaning agent in which the container is in fluid communication with the hybrid filter assembly, and providing a controller in communication with the hybrid filter assembly and the chemical cleaning system. The method also includes the steps of determining via the controller an operational efficiency of the filtration module at a predetermined interval of time and initiating via the controller a chemical cleaning mode to clean the hybrid filter assembly.Type: ApplicationFiled: November 4, 2024Publication date: May 8, 2025Inventors: Azur Dzindo, Thomas Johnson Safon, Caleb Ray, Anas Alhajeh, Alexander Smith, Donnie Fore, Eric Pinnell, Kenneth Koch, Stephanie Adams, Sean McEwan
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Publication number: 20250145495Abstract: A system for an aquatic application is provided in the form of a pump, a filtration system, a container, and a controller. The container is arranged to be in fluid communication with the filtration system and retains a chemical cleaning agent. The valve is positioned to be in fluid communication with the container and the filtration system. The controller is in communication with the valve. The controller is designed to determine a first permeability value associated with the filtration system at a first time period and initiates a cleaning procedure by providing the chemical cleaning agent to the filtration system when the first permeability value is below a permeability threshold value.Type: ApplicationFiled: November 4, 2024Publication date: May 8, 2025Inventors: Azur Dzindo, Thomas Johnson Safon, Caleb Ray, Anas Alhajeh, Alexander Smith, Donnie Fore, Eric Pinnell, Kenneth Koch, Dana Stephanie Royer Adams, Sean McEwan
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Patent number: 7433426Abstract: An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.Type: GrantFiled: April 23, 2004Date of Patent: October 7, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Zhubiao Zhu, Kenneth Koch, II, David J. C. Johnson
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Publication number: 20080176191Abstract: An endodontic cutting instrument for preparing root canal spaces of non-lengths standard length has a cutting portion that is equal to or greater than about 17 mm in length. The instrument is shaped to produce a conical root canal space with a uniform taper along the entire length of the conical root canal space, from an apex to a coronal opening thereof. The instrument may be part of an endodontic kit that includes multiple cutting instruments with respective cutting portions of different lengths and/or with respective cutting portions shaped to produce conical root canal spaces with different tapers. Optionally, the cutting instrument is provided with indicia for identifying its taper, the length of its cutting portion, or both. The indicia enables a user to quickly identify a suitable cone device for filling a root canal space prepared with the instrument.Type: ApplicationFiled: January 18, 2008Publication date: July 24, 2008Applicant: ENDODONTIC EDUCATIONAL SEMINARS, LLCInventors: Kenneth Koch, Dennis Brave
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Publication number: 20070222486Abstract: In one embodiment a circuit, comprises a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level, a driver comprising a first inverter, a second inverter, an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold, first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET, and second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power suType: ApplicationFiled: May 7, 2007Publication date: September 27, 2007Inventors: Kenneth Koch II, Mozammel Hossain
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Publication number: 20070168886Abstract: A virtual address bar user interface control is presented. The virtual address bar includes a plurality of interactive segments, each segment corresponding to a predetermined filter for selecting content in a computer file system. Collectively, the interactive segments represent a virtual address for selecting content. Selecting an interactive segment in the virtual address bar causes those segments subsequent to the selected segment to be removed from the virtual address bar. A user may select a peer filter for a segment to replace that segment's current filter and removes those segments subsequent to the updated segment. The virtual address bar can be selectively configured to operate as a conventional address bar, and reconfigured to operate as a virtual address bar. Additional filter segments are added to the end of the existing filter segments. Those existing filter segments that conflict with the added segment are removed from the virtual address bar.Type: ApplicationFiled: March 30, 2007Publication date: July 19, 2007Applicant: MICROSOFT CORPORATIONInventors: J. Hally, Kenneth Koch, Mark Ligameri, Jason Moore, Shaun Kaasten, Richard Banks, Michael Sheldon, David De Vorchik, Zeke Odins-Lucas, Patrice Miner
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Patent number: 7239185Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.Type: GrantFiled: February 13, 2004Date of Patent: July 3, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Koch, II, Mozammel Hossain
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Patent number: 7202702Abstract: A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.Type: GrantFiled: December 10, 2003Date of Patent: April 10, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Barry J. Arnold, Kenneth Koch, II, Philip L. Barnes
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Publication number: 20060234190Abstract: A glass ionomer or resin modified glass ionomer coated blank is combined with glass ionomer or resin modified glass ionomer to create an integral mono-block post. prefabricated glass ionomer or resin modified glass ionomer post (with or without a coated blank) is cemented into the root canal with glass ionomer or resin modified glass ionomer, thereby creating a mono-block post as well as a mono-block core. The glass ionomer or resin modified glass ionomer cement is bonded to the canal wall and also through the bonding of the cement to the post surface of similar material. An alternate methodology involves syringing glass ionomer or resin modified glass ionomer in a malleable, semi-solid state into the post preparation space and a glass ionomer or resin modified glass ionomer coated blank is then inserted into the canal to a distance substantially equal to the depth of the post preparation.Type: ApplicationFiled: March 31, 2006Publication date: October 19, 2006Inventors: Kenneth Koch, Dennis Brave
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Patent number: 7097455Abstract: An integral, one-piece silanated particle impregnated gutta percha core/cone technique employs a thin layer of a luting agent, such as glass ionomer cement with a machined gutta percha core/cone, precisely matches the preparation, thereby reducing leakage and achieving a hermetic seal. The hermetic seal is further enhanced by a mono-block bond that occurs between the silanated particles in the gutta percha and the appropriate chemical sealant. Optional cryogenic treatment of the gutta percha material changes its molecular weight, making it stiffer and conducive to forming an integral, one piece core/cone, without the need for a separate carrier core to install the tapered gutta percha core/cone within the root canal. Additionally, the tapered body of the core/cone may be reticulated in a slightly three dimensional texturized framework to increase surface area and therefore increase retention. Optional line demarcation indicia are also placed on the core/cone.Type: GrantFiled: December 22, 2003Date of Patent: August 29, 2006Assignees: Endodontic Educations Seminars LLC, Premier Dental Products Co.Inventors: Kenneth Koch, Dennis Brave, William McHale
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Publication number: 20060154212Abstract: An integral, one-piece silanated particle impregnated gutta percha core/cone technique employs a thin layer of a luting agent, such as glass ionomer cement with a machined gutta percha core/cone, precisely matches the preparation, thereby reducing leakage and achieving a hermetic seal. The hermetic seal is further enhanced by a mono-block bond that occurs between the silanated particles in the gutta percha and the appropriate chemical sealant. Optional cryogenic treatment of the gutta percha material changes its molecular weight, making it stiffer and conducive to forming an integral, one piece core/cone, without the need for a separate carrier core to install the tapered gutta percha core/cone within the root canal. Additionally, the tapered body of the core/cone may be reticulated in a slightly three dimensional texturized framework to increase surface area and therefore increase retention. Optional line demarcation indicia are also placed on the core/cone.Type: ApplicationFiled: March 13, 2006Publication date: July 13, 2006Inventors: Kenneth Koch, Dennis Brave, William McHale
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Publication number: 20060154213Abstract: An integral, one-piece gutta percha core/cone technique employs a thin layer of a luting agent, such as glass ionomer cement with a machined gutta percha core/cone, precisely matches the preparation, thereby reducing leakage and achieving a hermetic seal. Optional cryogenic treatment of the gutta percha material changes its molecular weight, making it stiffer and conducive to forming an integral, one piece core/cone, without the need for a separate carrier core to install the tapered gutta percha core/cone within the root canal. Additionally, the tapered body of the core/cone may be reticulated in a slightly three dimensional texturized framework to increase surface area and therefore increase retention. Optional line demarcation indicia are also placed on the core/cone. Additionally, the head of the core/cone can be gripped by a delivery vehicle clasp.Type: ApplicationFiled: March 13, 2006Publication date: July 13, 2006Inventors: Kenneth Koch, Dennis Brave
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Patent number: 7055114Abstract: Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.Type: GrantFiled: October 8, 2003Date of Patent: May 30, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Wayne Dervon Kever, Kenneth Koch, II
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Patent number: 7021936Abstract: An integral, one-piece silanated particle impregnated gutta percha core/cone technique employs a thin layer of a luting agent, such as glass ionomer cement with a machined gutta percha core/cone, precisely matches the preparation, thereby reducing leakage and achieving a hermetic seal. The hermetic seal is further enhanced by a mono-block bond that occurs between the silanated particles in the gutta percha and the appropriate chemical sealant. Optional cryogenic treatment of the gutta percha material changes its molecular weight, making it stiffer and conducive to forming an integral, one piece core/cone, without the need for a separate carrier core to install the tapered gutta percha core/cone within the root canal. Additionally, the tapered body of the core/cone may be reticulated in a slightly three dimensional texturized framework to increase surface area and therefore increase retention. Optional line demarcation indicia are also placed on the core/cone.Type: GrantFiled: December 22, 2003Date of Patent: April 4, 2006Inventors: Kenneth Koch, Dennis Brave
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Publication number: 20050238119Abstract: An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.Type: ApplicationFiled: April 23, 2004Publication date: October 27, 2005Inventors: Zhubiao Zhu, Kenneth Koch, David Johnson
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Publication number: 20050127947Abstract: A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Inventors: Barry Arnold, Kenneth Koch, Philip Barnes
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Patent number: 6882201Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.Type: GrantFiled: January 7, 2004Date of Patent: April 19, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Koch, II, Manuel Cabanas-Holmen, Daniel W. Krueger
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Publication number: 20050081167Abstract: Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.Type: ApplicationFiled: October 8, 2003Publication date: April 14, 2005Inventors: Wayne Kever, Kenneth Koch
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Patent number: 6803783Abstract: An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.Type: GrantFiled: January 31, 2003Date of Patent: October 12, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Zhubiao Zhu, Kenneth Koch, John R. Spencer
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Publication number: 20040169973Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET. The inverters, resistors and capacitors prevent the output stage PFET and NFET from being on simultaneously.Type: ApplicationFiled: February 13, 2004Publication date: September 2, 2004Inventors: Kenneth Koch, Mozammel Hossain