Patents by Inventor Kenneth Koch, II
Kenneth Koch, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7433426Abstract: An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.Type: GrantFiled: April 23, 2004Date of Patent: October 7, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Zhubiao Zhu, Kenneth Koch, II, David J. C. Johnson
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Publication number: 20070222486Abstract: In one embodiment a circuit, comprises a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level, a driver comprising a first inverter, a second inverter, an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold, first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET, and second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power suType: ApplicationFiled: May 7, 2007Publication date: September 27, 2007Inventors: Kenneth Koch II, Mozammel Hossain
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Patent number: 7239185Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.Type: GrantFiled: February 13, 2004Date of Patent: July 3, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Koch, II, Mozammel Hossain
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Patent number: 7202702Abstract: A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.Type: GrantFiled: December 10, 2003Date of Patent: April 10, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Barry J. Arnold, Kenneth Koch, II, Philip L. Barnes
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Patent number: 7055114Abstract: Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.Type: GrantFiled: October 8, 2003Date of Patent: May 30, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Wayne Dervon Kever, Kenneth Koch, II
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Patent number: 6882201Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.Type: GrantFiled: January 7, 2004Date of Patent: April 19, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Koch, II, Manuel Cabanas-Holmen, Daniel W. Krueger
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Patent number: 6778111Abstract: A system and method provide deglitch filtering. The system has a voltage-based deglitching filter and timing-based deglitching filter. The voltage-based deglitching filter connects with the timing-based deglitch filter, such that the output of the voltage-based deglitch filter connects to the input of the timing-based deglitch filter. The voltage-based deglitch filter is in feedback with the timing based deglitching filter.Type: GrantFiled: September 2, 2003Date of Patent: August 17, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Zhubiao Zhu, Kenneth Koch, II
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Patent number: 6759880Abstract: An integrated circuit driver includes an output stage having source drain paths of PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET.Type: GrantFiled: June 13, 2002Date of Patent: July 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Koch, II, Mozammel Hossain
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Patent number: 6753708Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.Type: GrantFiled: June 13, 2002Date of Patent: June 22, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Koch, II, Mozammel Hossain
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Patent number: 6734709Abstract: A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable rejection circuitry are used to provide a sufficient pulse width for sampling on the fly the one or more nodes when the one or more bus domain clocks require asynchronous operation. The sample on the fly circuitry is also operable to synchronously sample on the fly the one or more nodes.Type: GrantFiled: March 6, 2003Date of Patent: May 11, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Zhubiao Zhu, Kenneth Koch, II, J Robert Sims, III
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Patent number: 6404243Abstract: The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.Type: GrantFiled: January 12, 2001Date of Patent: June 11, 2002Assignee: Hewlett-Packard CompanyInventors: Kenneth Koch, II, William Weiner
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Patent number: 5692026Abstract: A shift register, circular pointer or ring counter presents a reduced capacitive load on the clock and shift signals used to control it. The device is constructed using one or more enhanced data cells. Each data cell has a data input, a data output, a clock input and a shift input. The data output of each cell is coupled to the data input of an adjacent cell. At least one pass-AND gate is provided for each cell. The pass-AND gate has a switching input and a switched input. The switching input operates to toggle the input capacitance of the switched input between a larger and a smaller value. The logical OR of the data input and data output of each cell is used to drive the switching input of the associated pass-AND gates for that cell. The switched input of the pass-AND gate is adapted to be coupled to the clock (or shift) signal, and the output of the pass-AND gate is coupled to the clock (or shift) input of the data cell.Type: GrantFiled: May 31, 1996Date of Patent: November 25, 1997Assignee: Hewlett-Packard CompanyInventors: Kenneth Koch, II, William J. Queen