Abstract: A precise digitally-controlled variable attenuation circuit for adjusting e attenuation of a signal in an external circuit includes a signal magnitude detector, a resistance adjustment control, and a resistance divider network. The signal magnitude detector has lower and upper threshold limits representing a desired range of attenuation and is operable to receive and compare a control signal with the lower and upper threshold limits, and, in response thereto, produce either a first signal if the control signal is less than the lower threshold limit or a second signal if the control signal is greater than the upper threshold limit. The adjustment control is capable of receiving the first and second signals and is operable to produce either a digital count-down signal in response to the first signal or a digital count-up signal in response to the second signal. The resistance divider network has a fixed resistance and a digitally-adjustable device with a variable resistance.

Abstract: A digital PLL circuit has a serial shift register receiving input pulses and producing time-delayed output pulses, a clock generator applying clock pulses to the shift register to drive it and set the phase shift of the output pulses, and a digitally-controlled potentiometer connected in series with the clock generator and being adjustable to change its resistance in increments in order to adjust the resistance of the clock generator and thereby set the frequency of the clock pulses applied to the shift register and the time delay produced by the shift register. A feedback control arrangement receives the same digital input pulses as received by the shift register and detects the periods of the input pulses by counting to produce control pulses proportional to the detected periods. A ROM unit stores a look-up table of values representing an array of different counts of increments by which the potentiometer resistance can be adjusted.