Abstract: A peripheral device is provided for a personal computer enabling the PC to provide the functions of a set-top box for television reception. Communication of television and control signals between the television and PC can be provided over the cable wiring already provided in the subscriber premises. Alternatively, wireless communication can be provided between the television and the PC. The invention obviates the need for a set-top box and the associated expense thereof. The television operations take place in the multitasking environment of the PC, so that the PC can be concurrently used for other applications.

Abstract: A peripheral device is provided for a personal computer enabling the PC to provide the functions of a set-top box for television reception. Communication of television and control signals between the television and PC can be provided over the cable wiring already provided in the subscriber premises. Alternatively, wireless communication can be provided between the television and the PC. The invention obviates the need for a set-top box and the associated expense thereof. The television operations take place in the multitasking environment of the PC, so that the PC can be concurrently used for other applications.

Abstract: The number of contact holes is reduced by fabricating the column select decode circuit as part of the array. The decode circuit includes four tiers of alternately arranged depletion mode and enhancement mode transistors, each tier receiving a different column address signal. The appropriate combination of signals connects a column of series connected driver transistors to the precharged control terminal of an isolation transistor. The output circuit of the isolation transistor is connected between the output line and ground. If all the driver transistors in the selected column are rendered conductive, the isolation transistor becomes non-conductive, permitting the output line to charge to a positive level.

Abstract: The memory circuit is formed by depositing spaced, parallel polysilicon strips on an insulating layer on the surface of the substrate. Spaced, parallel, elongated regions, which extend in a direction orthogonal to the strips, are formed in the substrate. Each elongated region comprises diffused segments (forming sources and drains) separated by non-diffused areas, masked by the strips, (forming channels). Spaced regions, extending parallel to the strips, are diffused to interconnect adjacent ones of the elongated regions, at intervals therealong. The strips are also subjected to the diffusion to produce conductivity appropriate for functioning as gates and gate interconnections. The elongated regions each form series connected enhancement mode devices of relatively low thresholds. Alternate elongated regions are subjected to a first implant to convert same into series connected depletion mode devices.

Abstract: Access time is reduced by isolating the relatively high impedance stack, formed of series connected driver transistors, from a relatively high capacitive output. The driver transistors are either enhancement mode or depletion mode transistors, depending upon the information to be represented thereby. An isolation transistor has its control terminal connected to the stack through a control node and its output circuit connected between the output node and ground. The output node is connected through a load to a positive voltage. A switched ground technique is used to charge the control node prior to addressing. During readout, if any of the series connected driver transistors in the selected stack are not rendered conductive, due to the level of the address signals applied thereto, the control node remains charged causing the isolation transistor to remain conductive and the output node is thus discharged. To increase density, multiple stacks are connected in parallel to a single isolation transistor.

Abstract: A read only memory in which the memory cells are single metal gate or silicon gate field effect transistors. Each FET has one of several different thresholds or states. The size or area of the FET gates at the surface of the semiconductor chip are substantially the same regardless of the cells threshold or state. The input to the gates is a ramp, and the cells are rendered conducting by the amplitude of the ramp at a given instant. The output of a cell is fed to several flip-flops, which are synchronized with the input ramp, thereby setting the flip-flops in accordance with the threshold or state of the cell. An encoder converts the output from the flip-flops to a bit binary signal. This permits a very high density ROM, e.g. 128K on a single chip. In another embodiment the input to the gates is a step, and the cells are all rendered conducting simultaneously. The amount of current drawn by each gate however, depends upon the doping in the gate region.

Abstract: Each bit of the register includes a plurality of active elements which perform as NOR logic gates. Each active element comprises an I.sup.2 L unit consisting of a bipolar inverter transistor and a bipolar injector transistor. Each element is cross-coupled with the previous element and the subsequent element, resulting in the static characteristic of the register. Data transfer control signals are generated which consist of a number of time synchronized pulse trains. Each pulse train is applied to a different one of the active elements in a bit and serves to energize same when positive (high). The shift register is bi-directional. The direction of data transfer is determined solely by the sequence of the data transfer control signals. The register is reset by causing all components of the control signal to simultaneously go low and thereafter restarting same in the proper sequence.