Abstract: A system for testing a launch vehicle comprises a flight control section including flight electronics, and a non-flight test section coupled to the flight control section. The non-flight test section comprises a first control module in communication with the flight electronics, and a second control module that provides redundancy in communication with the flight electronics. A first network serial interface is coupled to the first control module and configured to provide communication to ground support equipment, and a second network serial interface is coupled to the second control module and configured to provide communication to the ground support equipment. Only one of the first and second control modules is selected at a given point in time to send data to the flight control section. When a non-flight hardware error occurs in the selected control module, the other control module is automatically selected to send data to the flight control section.

Abstract: Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.

Abstract: Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.

Abstract: A system for testing a launch vehicle comprises a flight control section including flight electronics, and a non-flight test section coupled to the flight control section. The non-flight test section comprises a first control module in communication with the flight electronics, and a second control module that provides redundancy in communication with the flight electronics. A first network serial interface is coupled to the first control module and configured to provide communication to ground support equipment, and a second network serial interface is coupled to the second control module and configured to provide communication to the ground support equipment. Only one of the first and second control modules is selected at a given point in time to send data to the flight control section. When a non-flight hardware error occurs in the selected control module, the other control module is automatically selected to send data to the flight control section.

Abstract: Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.

Abstract: Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.