Patents by Inventor Kenneth Lik Kin Ho
Kenneth Lik Kin Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230367228Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Kenneth Lik Kin Ho, Chien-Jen Lai, Kenji Yamazoe, Xin Zhou, Danping Peng
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Patent number: 11754930Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.Type: GrantFiled: July 26, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kenneth Lik Kin Ho, Chien-Jen Lai, Kenji Yamazoe, Xin Zhou, Danping Peng
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Patent number: 11747786Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: GrantFiled: May 23, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
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Publication number: 20230005738Abstract: In a pattern formation method for a semiconductor device fabrication, an original pattern for manufacturing a photomask is acquired, a modified original pattern is obtained by performing an optical proximity correction on the original pattern, a sub-resolution assist feature (SRAF) seed map with respect to the modified original pattern indicating locations where an image quality is improved by an SRAF pattern is obtained, SRAF patterns are placed around the original pattern, the SRAF patterns and the modified original pattern are output as mask data, and the photo mask is manufactured using the mask data.Type: ApplicationFiled: March 31, 2022Publication date: January 5, 2023Inventors: Kenji YAMAZOE, Ping-Chieh WU, Hoi-Tou NG, Kenneth Lik Kin HO
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Publication number: 20220390854Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.Type: ApplicationFiled: July 26, 2022Publication date: December 8, 2022Inventors: Kenneth Lik Kin HO, Chien-Jen LAI, Kenji YAMAZOE, Xin ZHOU, Danping PENG
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Publication number: 20220291659Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: ApplicationFiled: May 23, 2022Publication date: September 15, 2022Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
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Patent number: 11435670Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.Type: GrantFiled: February 26, 2021Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kenneth Lik Kin Ho, Chien-Jen Lai, Kenji Yamazoe, Xin Zhou, Danping Peng
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Publication number: 20220276567Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Kenneth Lik Kin HO, Chien-Jen LAI, Kenji YAMAZOE, Xin ZHOU, Danping PENG
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Patent number: 11340584Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: GrantFiled: February 8, 2021Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
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Patent number: 11256176Abstract: A method includes determining a first transmission cross coefficient (TCC) operator of an optical system of a lithographic system based on an illumination source. The method includes sampling the illumination source by a first number of sampling points to produce a first discrete source and determining a second TCC operator based on the first discrete source. The method also includes determining an error between the first TCC operator and the second TCC operator. The method includes recursively adjusting the first number of sampling points to re-sample the illumination source and to re-determine the second TCC operator until the error is below a threshold level and a final discrete source and a final second TCC operator is determined.Type: GrantFiled: March 5, 2021Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Kenneth Lik Kin Ho
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Publication number: 20210181713Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: ApplicationFiled: February 8, 2021Publication date: June 17, 2021Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
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Patent number: 11003092Abstract: A method and an apparatus for computing feature kernels for optical model simulation are provided. In the method, a feature matrix mathematically describing a plurality of properties of an optical imaging system is identified. A sampling matrix comprising at least one vector serving as input to form a low-rank basis for the feature matrix is generated. The sampling matrix is iteratively multiplied by the feature matrix and a multiplication result is adaptively rescaled according to numerical stability until a convergence condition is met. The iteration results are used to form a reduced feature matrix. Decomposition values of the reduced feature matrix are computed and a plurality of feature kernels are extracted from the computed decomposition values.Type: GrantFiled: September 22, 2020Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kenneth Lik Kin Ho
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Patent number: 10915090Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: GrantFiled: June 1, 2020Date of Patent: February 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
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Publication number: 20210003923Abstract: A method and an apparatus for computing feature kernels for optical model simulation are provided. In the method, a feature matrix mathematically describing a plurality of properties of an optical imaging system is identified. A sampling matrix comprising at least one vector serving as input to form a low-rank basis for the feature matrix is generated. The sampling matrix is iteratively multiplied by the feature matrix and a multiplication result is adaptively rescaled according to numerical stability until a convergence condition is met. The iteration results are used to form a reduced feature matrix. Decomposition values of the reduced feature matrix are computed and a plurality of feature kernels are extracted from the computed decomposition values.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kenneth Lik Kin Ho
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Patent number: 10809629Abstract: A method and an apparatus for computing feature kernels for optical model simulation are provided. In the method, a feature matrix mathematically describing a plurality of properties of an optical imaging system is identified. A sampling matrix comprising at least one vector serving as input to form a low-rank basis for the feature matrix is generated. The sampling matrix is iteratively multiplied by the feature matrix and a multiplication result is adaptively rescaled according to numerical stability until a convergence condition is met. The iteration results are used to form a reduced feature matrix. Decomposition values of the reduced feature matrix are computed and a plurality of feature kernels are extracted from the computed decomposition values.Type: GrantFiled: May 28, 2019Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kenneth Lik Kin Ho
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Publication number: 20200293023Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
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Publication number: 20200073249Abstract: A method and an apparatus for computing feature kernels for optical model simulation are provided. In the method, a feature matrix mathematically describing a plurality of properties of an optical imaging system is identified. A sampling matrix comprising at least one vector serving as input to form a low-rank basis for the feature matrix is generated. The sampling matrix is iteratively multiplied by the feature matrix and a multiplication result is adaptively rescaled according to numerical stability until a convergence condition is met. The iteration results are used to form a reduced feature matrix. Decomposition values of the reduced feature matrix are computed and a plurality of feature kernels are extracted from the computed decomposition values.Type: ApplicationFiled: May 28, 2019Publication date: March 5, 2020Inventor: Kenneth Lik Kin Ho