Abstract: A program is executed using a call stack and shadow stack. The call stack includes frames having respective return addresses. The frames may also store variables and/or parameters. The shadow stack stores duplicates of the return addresses in the call stack. The call stack and the shadow stack are maintained by, (i) each time a function is called, adding a corresponding stack frame to the call stack and adding a corresponding return address to the shadow stack, and (ii) each time a function is exited, removing a corresponding frame from the call stack and removing a corresponding return address from the shadow stack. A backtrace of the program's current call chain is generated by accessing the return addresses in the shadow stack. The outputted backtrace includes the return addresses from the shadow stack and/or information about the traced functions that is derived from the shadow stack's return addresses.

Abstract: A multilayer moisture barrier film includes a first outer layer, a second outer layer, and at least one desiccant-containing inner layer between the first and second outer layers. The inner layer can have cavities with which the desiccant particles are in communication.

Abstract: PSA Label Rolls using spent liners and a novel continuous process to convert a stack of face material into a roll of label stock by affixing adhesive coated face material onto a liner. Provides a process to recycle waste liner from conventional roll label stock application machines. Uses an ultra-high solids adhesive that needs no drying. Roll label stock made by such a process provides large cost savings and beneficial environmental impact.

Abstract: A multilayer moisture barrier film includes a first outer layer, a second outer layer, and at least one desiccant-containing inner layer between the first and second outer layers. The inner layer can have cavities with which the desiccant particles are in communication.

Abstract: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.

Abstract: A testing system and method for an arithmetic logic unit are provided. The system includes: a control unit, a data providing unit, a first input unit, a second input unit, an arithmetic logic unit, an expected result unit, a comparator and a test result storage unit. The control unit controls the testing process. The data providing unit provides data for the first input unit, the second input unit and the expected result unit. The first input unit and the second input unit provide test data for the arithmetic logic unit. The arithmetic logic unit performs an operation and provides an operation result for the comparator. The expected result unit generates an expected result and provides the expected result of this round of testing for the comparator. The comparator compares the operation result with the expected result, and provides a comparison result for the test result storage unit.

Abstract: Processing and use of ultra-high solids formulations wherein no drying step is needed for the formulation to be incorporated in a wide variety of applications. Adhesives, top-coatings, sealants, fasteners are amongst the use areas.

Abstract: A method for assisting operations of a processor core coupled to a first memory and a second memory includes: examining instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information of the instructions, and creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling one or more instructions from the first memory to the second memory based on one or more tracks from the plurality of tracks before the processor core starts executing the instructions, such that the processor core fetches the instructions from the second memory for execution. Filling the instructions further includes pre-fetching from the first memory to the second memory instruction segments containing the instructions corresponding to at least two levels of branch target instructions based on the one or more tracks.

Abstract: A testing system and method for an arithmetic logic unit are provided. The system includes: a control unit, a data providing unit, a first input unit, a second input unit, an arithmetic logic unit, an expected result unit, a comparator and a test result storage unit. The control unit controls the testing process. The data providing unit provides data for the first input unit, the second input unit and the expected result unit. The first input unit and the second input unit provide test data for the arithmetic logic unit. The arithmetic logic unit performs an operation and provides an operation result for the comparator. The expected result unit generates an expected result and provides the expected result of this round of testing for the comparator. The comparator compares the operation result with the expected result, and provides a comparison result for the test result storage unit.

Abstract: A high-performance data cache system and method is provided for facilitating operation of a processor core. The method includes examining instructions to generate stride length of base register value corresponding to every data access instruction; based on the stride length of base register value, calculating possible a data access address of the data access instruction to be executed next time; based on the calculated the possible data access address of the data access instruction to be executed next time, prefetching data and filling the data to cache memory before the processor core accesses the data. The processor core may access directly the needed data from the cache memory almost every time, thus getting very high cache hit rate.

Abstract: A method for assisting operations of a processor core coupled to a first memory and a second memory includes: examining instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information of the instructions, and creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling one or more instructions from the first memory to the second memory based on one or more tracks from the plurality of tracks before the processor core starts executing the instructions, such that the processor core fetches the instructions from the second memory for execution. Filling the instructions further includes pre-fetching from the first memory to the second memory instruction segments containing the instructions corresponding to at least two levels of branch target instructions based on the one or more tracks.

Abstract: A method for facilitating operation of a processor core is provided. The method includes: examining instructions being filled from a second instruction memory to a third instruction memory, extracting instruction information containing at least branch information and generating a stride length of base register corresponding to every data access instruction; creating a plurality of tracks based on the extracted instruction; filling at least one or more instructions that are likely to be executed by the processor core based on one or more tracks from the plurality of tracks from a first instruction memory to the second instruction memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second instruction memory to the third instruction memory; calculating possible data access address of the data access instruction to be executed next time based on the stride length of the base register.

Abstract: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.

Abstract: A rigid tubular mouthpiece for a smoking article may include a cushioning wrapping material thereabout. The wrapping material may be configured to form several layers, encompassed by a polymeric label, which may include indicia. The wrapping material will provide a lower durometer, as applied, than the unwrapped mouthpiece, which may be incorporated as part of a smoking article.

Abstract: An information processing system is provided. The information processing system includes a processor used to obtain information, a memory used to store the information and output an information block based on a received address; and a scanner used to generate an address based on the current information block and to provide the address to the memory, where the current information block is the information block currently outputted from the memory. Thus, the speed for obtaining the information block by the processor (information block requested device) is further improved, and the execution speed of the processor and the information processing system is improved.

Abstract: A process for making an ultra high solids emulsion adhesive that is coatable and dryable at room temperature. The process consists of increasing solids using a phase inversion process to accomplish the addition of increased solids into aqueous formulations thereby obtaining emulsion pressure sensitive adhesives with solids content in excess of 60%.

Abstract: A process for making an ultra high solids emulsion adhesive that is coatable and dryable at room temperature. The process consists of increasing solids using a phase inversion process to accomplish the addition of increased solids into aqueous formulations thereby obtaining emulsion pressure sensitive adhesives with solids content in excess of 60%.

Abstract: A method and system for providing targeted advertising to consumers is disclosed. Identifying information for a consumer is received. A credit attribute for the consumer using the identifying information is retrieved. At least one advertisement is stored in which each advertisement includes a corresponding credit attribute range. An advertisement for presentation to the consumer is selected based on the credit attribute of the consumer and the credit attribute range of the advertisement.

Abstract: A photo album is provided having an ink-receptive coating on a surface of the photo album. A user may write text or draw pictures on the surface with an ink pen, such as with a gel-based ink pen. The ink-receptive coating protects the ink from smudging or smearing after the ink has dried. Consequently, the text and/or picture is durable. The writable or drawable surface may be the front or back exterior surface, and/or an interior surface.

Abstract: A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.