Patents by Inventor Kenneth Louie
Kenneth Louie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200294598Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reducing routing signals. An apparatus includes a first block decoder circuit that senses bad block data of a first latch circuit corresponding to a first memory block and couple the bad block data onto a bus. An apparatus includes a comparator circuit that compares the bad block data against a reference, sets a bad block flag, and routes the bad block flag on a routing line across an array of storage elements. An apparatus includes a second block decoder circuit that receives the bad block flag from the routing line, determines a condition of the first memory block based on the bad block flag, and determines a generation of a block selection signal for selecting a second memory block.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Inventors: Kenneth Louie, Seok Tae Kim, Arka Ganguly, Qui Nguyen
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Publication number: 20200265899Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Applicant: SanDisk Technologies LLCInventors: Kenneth Louie, Anirudh Amarnath
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Patent number: 10643713Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.Type: GrantFiled: February 8, 2019Date of Patent: May 5, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Kenneth Louie, Anirudh Amarnath
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Patent number: 10255978Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.Type: GrantFiled: May 8, 2017Date of Patent: April 9, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Kenneth Louie, Qui Nguyen, Tai-yuan Tseng, Jong Yuh, Ohwon Kwon
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Publication number: 20190066788Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reduced routing signals. An apparatus includes a generator circuit that generates switch gate voltages for two or more word line switches. Two or more word line switches are on opposite sides of an array of memory elements and are for coupling word line voltages to word lines. An apparatus includes a word line switch circuit that supplies switch gate voltages to two or more word line switches. An apparatus includes a transistor control circuit that supplies select gate voltages to two or more select gates. Two or more select gates control select gate drain transistors. Select gate voltages are different from switch gate voltages. Select gate voltages and switch gate voltages are both based on a routing line voltage on a routing line that extends across an array of memory elements.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Applicant: SanDisk Technologies LLCInventors: KENNETH LOUIE, QUI NGUYEN
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Publication number: 20180322928Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventors: Kenneth Louie, Qui Nguyen, Tai-yuan Tseng, Jong Yuh, Ohwon Kwon
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Patent number: 10115440Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: GrantFiled: June 16, 2017Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
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Patent number: 10043558Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: GrantFiled: June 20, 2017Date of Patent: August 7, 2018Assignee: SanDisk Technologies LLCInventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Publication number: 20180197586Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: ApplicationFiled: June 16, 2017Publication date: July 12, 2018Applicant: SanDisk Technologies LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
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Patent number: 9947395Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: GrantFiled: April 13, 2017Date of Patent: April 17, 2018Assignee: SanDisk Technologies LLCInventors: Kenneth Louie, Man Mui
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Publication number: 20170309340Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: ApplicationFiled: June 20, 2017Publication date: October 26, 2017Applicant: SanDisk Technologies LLCInventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Publication number: 20170309338Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: ApplicationFiled: April 26, 2016Publication date: October 26, 2017Applicant: SanDisk Technologies Inc.Inventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Patent number: 9792995Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: GrantFiled: April 26, 2016Date of Patent: October 17, 2017Assignee: SanDisk Technologies LLCInventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Publication number: 20170221556Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Inventors: Kenneth Louie, Man Mui
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Patent number: 9627046Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: GrantFiled: March 2, 2015Date of Patent: April 18, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Kenneth Louie, Man Mui
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Patent number: 9536617Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.Type: GrantFiled: October 30, 2015Date of Patent: January 3, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma
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Patent number: 9490020Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.Type: GrantFiled: May 16, 2016Date of Patent: November 8, 2016Assignee: SanDisk Technologies LLCInventors: Kenneth Louie, Khanh Nguyen
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Patent number: 9472298Abstract: Determining dynamic read levels for memory cells is disclosed. A group of memory cells may be read at a pair of reference levels. Results of reading the group at the pair of reference levels are compared while the group is read at a different reference level. By comparing the results of reading the group at the pair of reference levels while reading the group at a different reference level, time is saved. Note that the reading and comparing can be repeated for other pairs of reference levels. The storage device may determine an adjusted read level based on the comparisons of the results for the different pairs of reference levels. The memory cells may be read at a set of reference levels. A voltage on a word line is not back down to ground between the reads in one aspect, which saves considerable time.Type: GrantFiled: October 26, 2015Date of Patent: October 18, 2016Assignee: SanDisk Technologies LLCInventors: Kenneth Louie, Chang Siau, Gopinath Balakrishnan, Kapil Verma, Grishma Shah
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Publication number: 20160293264Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.Type: ApplicationFiled: October 30, 2015Publication date: October 6, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma
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Publication number: 20160260476Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: ApplicationFiled: March 2, 2015Publication date: September 8, 2016Inventors: Kenneth Louie, Man Mui