Abstract: Systems and methods for creating unique device identification for semiconductor devices are described. In some embodiments, a method may include receiving a wafer identification mark printed on a semiconductor wafer having a plurality of dies fabricated thereon; receiving a leadframe identification mark printed on a leadframe configured to receive the plurality of dies during a die attach operation; and for each of the plurality of dies: (a) recording a wafer location of a given die prior to the die attach operation; (b) recording a leadframe location of the given die after the die attach operation; (c) creating a device identification mark for the given die based upon the wafer identification mark, the leadframe identification mark, the wafer location, and the leadframe location; and (d) printing the device identification mark on a package of the given die.

Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.

Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Abstract: Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.

Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.

Abstract: A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.

Abstract: A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.

Abstract: Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.

Abstract: A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.

Abstract: A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).

Abstract: A method for enabling test vectors to be generated for a customer designed integrated circuit (16) having an embedded vendor circuit (12) is disclosed. The embedded vendor circuit (12) has a proprietary circuit (18) and a nonproprietary circuit (20). At least one pseudo input is defined (62) to represent a portion of the nonproprietary circuit (20) to emulate the nonproprietary circuit output. An output node (31) of the embedded vendor circuit (12) to which an input of the customer designed circuit (14) is connectable is identified (64). A test netlist is created (66) which represents circuitry that produces output states at the output node (31) which would be generated by the embedded vendor circuit thereat (12).

Abstract: A method for enabling test vectors to be generated for a customer designed integrated circuit having an embedded vendor circuit is disclosed. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.

Abstract: A method for enabling test vectors to be generated for a customer designed integrated circuit (16) having an embedded vendor circuit (12) is disclosed. The embedded vendor circuit (12) has a proprietary circuit (18) and a nonproprietary circuit (20). At least one pseudo input is defined (62) to represent a portion of the nonproprietary circuit (20) to emulate the nonproprietary circuit output . An output node (31) of the embedded vendor circuit (12) to which an input of the customer designed circuit (14) is connectable is identified (64). A test netlist is created (66) which represents circuitry that produces output states at the output node (31) which would be generated by the embedded vendor circuit thereat (12).

Abstract: A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as 32, are minimized through the use of constant input data.

Abstract: A system (13) is provided for structurally testing an integrated circuit device, The system includes a signature analyzer (14) operable to compress test results received from the integrated circuit device into a signature. A control device (20) is coupled to the signature analyzer (14), The control device (20) is operable to enable the compression operation of the signature analyzer (14) when the test results contain known states and disable the compression operation when the test results contain unknown states.