Patents by Inventor Kenneth M. Sautter
Kenneth M. Sautter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8361548Abstract: A process for the coating of substrates comprising insertion of a substrate into a process oven, plasma cleaning of the substrate, rehydration of the substrate, dehydration of the substrate, withdrawal of a metered amount of one or more chemicals from one or more chemical reservoirs, vaporizing the withdrawn chemicals in one or more vapor chambers, and transfer of the vaporized chemicals into a process oven, thereby reacting with the substrate. An apparatus for the coating of substrates comprising a process oven, a gas plasma generator, a metered chemical withdrawal subsystem, and a vaporization subsystem.Type: GrantFiled: August 20, 2008Date of Patent: January 29, 2013Assignee: Yield Engineering Systems, Inc.Inventors: William A. Moffat, Kenneth M. Sautter
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Publication number: 20100203260Abstract: A process for the coating of substrates comprising insertion of a substrate into a process oven, plasma cleaning of the substrate, rehydration of the substrate, dehydration of the substrate, withdrawal of a metered amount of one or more chemicals from one or more chemical reservoirs, vaporizing the withdrawn chemicals in one or more vapor chambers, and transfer of the vaporized chemicals into a process oven, thereby reacting with the substrate. An apparatus for the coating of substrates comprising a process oven, a gas plasma generator, a metered chemical withdrawal subsystem, and a vaporization subsystem.Type: ApplicationFiled: August 20, 2008Publication date: August 12, 2010Inventors: William A. Moffat, Kenneth M. Sautter
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Patent number: 6486528Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.Type: GrantFiled: August 23, 1999Date of Patent: November 26, 2002Assignee: Vertical Circuits, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 6255726Abstract: An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.Type: GrantFiled: August 21, 1997Date of Patent: July 3, 2001Assignee: Cubic Memory, Inc.Inventors: Alfons Vindasius, Kenneth M. Sautter
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Patent number: 6188126Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment, includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.Type: GrantFiled: April 24, 1997Date of Patent: February 13, 2001Assignee: Cubic Memory Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 6177296Abstract: A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.Type: GrantFiled: March 22, 1999Date of Patent: January 23, 2001Assignee: Cubic Memory Inc.Inventors: Alfons Vindasius, Kenneth M. Sautter
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Patent number: 6134118Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.Type: GrantFiled: April 3, 1997Date of Patent: October 17, 2000Assignee: Cubic Memory Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 6124633Abstract: An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.Type: GrantFiled: August 22, 1997Date of Patent: September 26, 2000Assignee: Cubic MemoryInventors: Alfons Vindasius, Kenneth M. Sautter
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Patent number: 6080596Abstract: A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.Type: GrantFiled: August 22, 1997Date of Patent: June 27, 2000Assignee: Cubic Memory Inc.Inventors: Alfons Vindasius, Kenneth M. Sautter
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Patent number: 5994170Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.Type: GrantFiled: April 25, 1997Date of Patent: November 30, 1999Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5936302Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.Type: GrantFiled: April 25, 1997Date of Patent: August 10, 1999Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5891761Abstract: A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.Type: GrantFiled: August 22, 1997Date of Patent: April 6, 1999Assignee: Cubic Memory, Inc.Inventors: Alfons Vindasius, Kenneth M. Sautter
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Patent number: 5837566Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.Type: GrantFiled: April 24, 1997Date of Patent: November 17, 1998Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5698895Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.Type: GrantFiled: January 20, 1995Date of Patent: December 16, 1997Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5675180Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.Type: GrantFiled: June 23, 1994Date of Patent: October 7, 1997Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5661087Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.Type: GrantFiled: June 7, 1995Date of Patent: August 26, 1997Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5657206Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.Type: GrantFiled: January 19, 1995Date of Patent: August 12, 1997Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 4977330Abstract: An in-line photoresist thickness measuring device wherein a plurality of projection optical fibers are disposed over a wafer processing track for illuminating portions of a wafer as the wafer proceeds along the track. The light scattered back from each illuminated portion is detected by a corresponding plurality of pickup optical fibers and communicated to an optical fiber multiplexer. The multiplexer sequentially selects the optical signal from each pickup optical fiber and communicates the light from the selected pickup optical fiber to a spectrometer. The spectrometer simultaneously diffuses the scattered light into a plurality of light bands, each light band having a different wavelength. The plurality of light bands are projected in parallel onto a pin diode array which acts as a photodetector. The electrical signals generated by each pin diode in response to the incident light bands are communicated to a processor which calculates resist thickness for each illuminated portion of the wafer.Type: GrantFiled: February 13, 1989Date of Patent: December 11, 1990Inventors: Tom W. Batchelder, Kenneth M. Sautter, Gary H. Memovich
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Patent number: 4647172Abstract: In the resist development method disclosed herein, the spin development of a resist coating on the surface of a semiconductor wafer is monitored by measuring light scattered back from the wafer surface from an incandescent source. During development, the sensed light level oscillates due to optical fringing caused by the thinning of the resist layer in the exposed areas and the fringe generated oscillation essentially stops when the development breaks through in the exposed areas. By comparing sample data obtained from the sensed light level with template data representing a known or characteristic behavior, a control point corresonding to the last fringe may be determined. Development is then terminated a calculated time after the control point.Type: GrantFiled: May 17, 1985Date of Patent: March 3, 1987Assignee: GCA CorporationInventors: William T. Batchelder, John A. Piatt, Kenneth M. Sautter