Patents by Inventor Kenneth Malich
Kenneth Malich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7318115Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: GrantFiled: August 27, 2003Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Patent number: 7287148Abstract: An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.Type: GrantFiled: August 28, 2003Date of Patent: October 23, 2007Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Patent number: 7233166Abstract: Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.Type: GrantFiled: August 27, 2003Date of Patent: June 19, 2007Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Publication number: 20050076194Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 28, 2003Publication date: April 7, 2005Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle Philhower, Manoj Mehta, Kenneth Malich
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Publication number: 20040236896Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 27, 2003Publication date: November 25, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
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Patent number: 6766446Abstract: A loop buffer for storing and holding instructions executed within loops for digital signal processing. Control logic detects the beginning and ending of a loop to signal the loop buffer control logic to start instruction execution in a cyclical fashion using the instructions stored within the loop buffer. After completion of the required number of loops, the instructions in the loop buffer are overwritten with new instructions until the next loop is to be processed. The loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.Type: GrantFiled: February 3, 2003Date of Patent: July 20, 2004Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathipillai, Kenneth Malich
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Patent number: 6732203Abstract: In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.Type: GrantFiled: March 29, 2002Date of Patent: May 4, 2004Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
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Publication number: 20040078612Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 21, 2003Publication date: April 22, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
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Publication number: 20040078608Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 29, 2003Publication date: April 22, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
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Publication number: 20040039952Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 27, 2003Publication date: February 26, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
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Publication number: 20030163679Abstract: A loop buffer for storing and holding instructions executed within loops for digital signal processing. Control logic detects the beginning and ending of a loop to signal the loop buffer control logic to start instruction execution in a cyclical fashion using the instructions stored within the loop buffer. After completion of the required number of loops, the instructions in the loop buffer are overwritten with new instructions until the next loop is to be processed. The loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.Type: ApplicationFiled: February 3, 2003Publication date: August 28, 2003Inventors: Kumar Ganapathy, Ruban Kanapathipillai, Kenneth Malich
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Patent number: 6598155Abstract: A loop buffer for storing and holding instructions executed within loops for digital signal processing. Control logic detects the beginning and ending of a loop to signal the loop buffer control logic to start instruction execution in a cyclical fashion using the instructions stored within the loop buffer. After completion of the required number of loops, the instructions in the loop buffer are overwritten with new instructions until the next loop is to be processed. The loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.Type: GrantFiled: January 31, 2000Date of Patent: July 22, 2003Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathipillai, Kenneth Malich
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Publication number: 20030056134Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: March 29, 2002Publication date: March 20, 2003Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich