Abstract: An efficient method of compositing planes onto a target surface using a computing device with graphics processing capability is disclosed. The method includes partitioning the target surface, on which planes are composited, into partitions. Each one of the partitions contains connected pixels to be formed by compositing an identical subset of the planes to be composited. Each partition is associated with a corresponding subset of the planes. Each partition and its corresponding set of associated planes are then provided to a graphics processor for composition, using exemplary software components including an application programming interface, a library and device driver software. An image is formed on the target surface by compositing each partition. Using the disclosed method, a single pass through stages of the graphics pipeline for the graphics processor is sufficient to composite multiple planes to form an image on the target surface.

Abstract: The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available.

Abstract: An efficient method of compositing planes onto a target surface using a computing device with graphics processing capability is disclosed. The method includes partitioning the target surface, on which planes are composited, into partitions. Each one of the partitions contains connected pixels to be formed by compositing an identical subset of the planes to be composited. Each partition is associated with a corresponding subset of the planes. Each partition and its corresponding set of associated planes are then provided to a graphics processor for composition, using exemplary software components including an application programming interface, a library and device driver software. An image is formed on the target surface by compositing each partition. Using the disclosed method, a single pass through stages of the graphics pipeline for the graphics processor is sufficient to composite multiple planes to form an image on the target surface.

Abstract: A method and system for prevention of unauthorized access to multimedia data are disclosed herein. A tamper-resistant system having a software driver, a peripheral device, and a system memory is used to encrypt sensitive routines used by the software driver. The software driver is used to interface between one component of the system, such as a processor, and a peripheral device, such as a graphics chip. The driver incorporates one or more sensitive routines, that if divulged, could possibly allow an unauthorized party access to data processed by the software driver. Accordingly, in one embodiment, the sensitive routines are stored in an encrypted format with the driver. To access a sensitive routine, the driver submits the associated encrypted routine to the peripheral device, as well as a decryption method, if desired, where it is decrypted and stored in a plaintext format in a location, such as system memory, accessible to both the driver and the peripheral device.

Abstract: A video playback circuit receives flip call information and vertical synchronization information, and in response determines a pause mode and a playback mode. Flip call information, as is known in the art, provides an indication for flipping between a front buffer and a back buffer, in order to facilitate rendering into one buffer while rasterizing out of the other buffer. Vertical synchronization information describes the completion of rasterizing an image onto a display, and often occurs at periodic intervals, e.g., 60 Hz, 100 Hz. The video playback circuit further includes a pause/playback-based frame buffer pointer information generator. The pause/playback-based frame buffer pointer information generator generates unfiltered frame buffer pointer information when in the pause mode. Otherwise, the pause/playback-based frame buffer pointer information generator generates filtered frame buffer pointer information when in the playback mode.

Abstract: The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available.

Abstract: A video playback circuit receives flip call information and vertical synchronization information, and in response determines a pause mode and a playback mode. Flip call information, as is known in the art, provides an indication for flipping between a front buffer and a back buffer, in order to facilitate rendering into one buffer while rasterizing out of the other buffer. Vertical synchronization information describes the completion of rasterizing an image onto a display, and often occurs at periodic intervals, e.g., 60 Hz, 100 Hz. The video playback circuit further includes a pause/playback-based frame buffer pointer information generator. The pause/playback-based frame buffer pointer information generator generates unfiltered frame buffer pointer information when in the pause mode. Otherwise, the pause/playback-based frame buffer pointer information generator generates filtered frame buffer pointer information when in the playback mode.

Abstract: A system and method for handling errors is provided. Errors related to the processing and storage of inverse discrete cosine transform (IDCT) image data cause hardware to become stalled. Stalled hardware may result in multiple image frames being dropped or lost during video playback. To avoid the stalling of hardware, the hardware is used to analyze the data being processed. Data being stored may be analyzed to determine if any error-characteristics, such as overflow or underflow, are present in the storing of the data. The data is manipulated to avoid stalling due to the error-characteristics.

Abstract: Methods and systems are provided for encrypting data from a plurality of multimedia devices. A driver initiates authentication for the plurality of multimedia applications. The driver assigns a key registers to each of the applications, based on available key registers. The applications use generated encryption key values to send data to be decrypted by their assigned key registers. The driver notifies video processing hardware of encryption seed keys to determine the generated encryption key values and hardware stores the value of corresponding decryption keys the assigned key registers. Each register can be used to exclusively decrypt data from an application of the plurality of applications. The driver directs the encrypted data from the applications to the video processing hardware. The video processing hardware decrypts the data and processes it into image data accordingly.

Abstract: A method and system for prevention of unauthorized access to multimedia data are disclosed herein. A tamper-resistant system having a software driver, a peripheral device, and a system memory is used to encrypt sensitive routines used by the software driver. The software driver is used to interface between one component of the system, such as a processor, and a peripheral device, such as a graphics chip. The driver incorporates one or more sensitive routines, that if divulged, could possibly allow an unauthorized party access to data processed by the software driver. Accordingly, in one embodiment, the sensitive routines are stored in an encrypted format with the driver. To access a sensitive routine, the driver submits the associated encrypted routine to the peripheral device, as well as a decryption method, if desired, where it is decrypted and stored in a plaintext format in a location, such as system memory, accessible to both the driver and the peripheral device.

Abstract: A system and method for handling errors is provided. Errors related to the processing and storage of inverse discrete cosine transform (IDCT) image data cause hardware to become stalled. Stalled hardware may result in multiple image frames being dropped or lost during video playback. To avoid the stalling of hardware, the hardware is used to analyze the data being processed. Data being stored may be analyzed to determine if any error-characteristics, such as overflow or underflow, are present in the storing of the data. The data is manipulated to avoid stalling due to the error-characteristics.

Abstract: A secondary ignition switch system that connects to a conventional ignition switch system of a vehicle to provide a security function. The secondary ignition system includes a dashboard mounted double-pole-double-throw (DPDT) switch and a key operated secondary ignition switch. The DPDT switch controls the operation of the primary and secondary ignition switches. To start the engine the DPDT is set to a position to power the secondary ignition switch, such that the engine can be started by turning a secondary key. However, based on the interconnection of the ignition switches the steering column of the vehicle remains locked. Only until the operator uses the primary key to unlock the steering assembly can the car be driven. This system enables the engine of a vehicle to run including powering the accessory circuit (for heating/cooling and power accessories) to warm a vehicle in cold climates with minimized risk since the steering assembly remains locked.