Abstract: A method for inline bus data compression and decompression is disclosed. In one embodiment, data is selected for transfer via a data bus, the data is divided into byte sized divisions of the bus width, and each byte is compressed by an individual compression engine. The data is then properly sequenced, aligned and recombined and further transmitted in its compressed state. When required to be decompressed, the compressed data is again divided into bytes of compressed data, each byte being decompressed individually, and then restored to the bus in its uncompressed form, in essence, in the reverse order of the compression process.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. One embodiment uses a memory table having entries to locate data residing in different types of storage areas, such as physical memory, hard disc, file servers, storage devices, etc. Upon a program accessing memory for a particular piece of data, the memory table translates the data's physical address to an address used to find the table entry pointing to the requested data. In one embodiment, if the data is in physical memory, then the requested data is returned to the program. However, if the data is not in physical memory and it is determined that the data will be used frequently, then the data, in addition to being returned, is also brought to the physical memory for later use. This is because accessing the data from physical memory usually takes less time than accessing the data from other storage devices.

Abstract: In a method for optimizing performance in a memory system, a data structure configured to provide at least one free block of memory is received in the memory system. At least one bucket of memory is released in a swap device of the memory system corresponding to at least one free block of memory provided by the data structure.

Abstract: A method and system providing dynamic allocation of memory through hardware is disclosed. An embodiment provides for a multi-processor system providing for a secure partitioned memory. The system comprises a processor(s), a hardware implemented memory router coupled to the processor(s), and memory coupled to the memory router. The memory router stores memory partition information, which describes the memory allocated to the processor(s). Furthermore, the memory router maps a memory access request from a processor to an address in the memory.

Abstract: A multi-processor system using distributed memory is provided with a cache of history counters located within each memory controller. Each entry of the cache of history counters represents one page in memory that has the potential to increase system performance by migrating or replicating to other memory locations. The cache of history counters permits creating histories of local memory accesses by remote processors for purposes of dynamic page placement.

Abstract: The present invention pertains to a system for performing data compression/decompression. The system may have a memory controller with compression/decompression logic. A first memory array may be coupled to the memory controller via a first bus and a second memory array may be coupled to the memory controller via a second bus. The system may also have logic for directing the transfer of data from the first memory array via the first bus to be processed by the compression/decompression logic and then transferred to the second memory array via the second bus.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various physical locations, and a relocation table is created with entries used to locate these blocks. To access memory for a particular piece of data, a program first uses a virtual address of the data, which, through a translation look-aside buffer, is translated into a physical address within the computer system. Using the relocation table, the physical address is then translated to a relocation address that identifies the relocation block containing the requested data. From the identified relocation block, the data is returned to the program.

Abstract: A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.

Abstract: A multiprocessor system, where the latencies to access areas of memory have different values, provides the capability of having the operating system use large page sizes while dynamic page placement manipulates subsets of the large pages without affecting translation look-aside buffers in the processors. A sub-page support structure is inserted between the processor and the network interface to remote memory that on a remote memory access determines if a local copy of the data exists and, if it does, to change the remote access to a local access. Where a sub-page in a remote memory has been migrated to a third UMA cell, the sub-page support structure also instructs the processor of the new memory location or passes the access along to the correct UMA cell.

Abstract: A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: The present invention pertains to a system for performing data compression/decompression. The system may have a memory controller with compression/decompression logic. A first memory array may be coupled to the memory controller via a first bus and a second memory array may be coupled to the memory controller via a second bus. The system may also have logic for directing the transfer of data from the first memory array via the first bus to be processed by the compression/decompression logic and then transferred to the second memory array via the second bus.

Abstract: A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.

Abstract: A method and system for parallel fetch and decompression of compressed data blocks is disclosed. A method first accesses a table of pointers specifying the location of compressed data to obtain a pointer. Using the pointer, the method reads a pointer in the first block of data, the pointer specifying the location of the next block of compressed data in a chain of compressed data blocks. The method also transfers the rest of the first compressed data block to be decompressed. The method then fetches the next compressed data block using the second pointer while decompressing the first compressed data block. Using a pointer in each successive compressed data block in the chain, the method pre-fetches the next compressed data block while the previous compressed data block is being decompressed.

Abstract: In a method for optimizing performance in a memory system, a data structure configured to provide at least one free block of memory is received in the memory system. At least one bucket of memory is released in a swap device of the memory system corresponding to at least one free block of memory provided by the data structure.

Abstract: A computer system with mechanisms for avoiding mapping conflicts in a translation look-aside buffer. A memory manager in the computer system allocates a virtual address to a process by determining a set of previously allocated virtual addresses for the process and selecting the virtual address such that the mapping of the virtual address to the translation look-aside buffer does not conflict with any of the previously allocated virtual addresses.

Abstract: A method of operating a data processing system having a main memory divided into memory pages that are swapped into and out of main memory when the main memory becomes short. The data processing system has an operating system that sends page store commands specifying memory pages to be stored in a swap file and page retrieve commands specifying memory pages to be retrieved from the swap file and stored in the main memory. The present invention provides a swap driver that utilizes compression code for converting one of the memory pages that is to be swapped out of main memory to a compressed memory page. The data processing memory includes a compressed page region that is used to store the compressed memory pages. A page table in the compressed page region specifies the location of each compressed page and the page address corresponding to that page.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. One embodiment uses a memory table having entries to locate data residing in different types of storage areas, such as physical memory, hard disc, file servers, storage devices, etc. Upon a program accessing memory for a particular piece of data, the memory table translates the data's physical address to an address used to find the table entry pointing to the requested data. In one embodiment, if the data is in physical memory, then the requested data is returned to the program. However, if the data is not in physical memory and it is determined that the data will be used frequently, then the data, in addition to being returned, is also brought to the physical memory for later use. This is because accessing the data from physical memory usually takes less time than accessing the data from other storage devices.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various physical locations, and a relocation table is created with entries used to locate these blocks. To access memory for a particular piece of data, a program first uses a virtual address of the data, which, through a translation look-aside buffer, is translated into a physical address within the computer system. Using the relocation table, the physical address is then translated to a relocation address that identifies the relocation block containing the requested data. From the identified relocation block, the data is returned to the program.