Patents by Inventor Kenneth Mednick

Kenneth Mednick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for implementing parallel processing of electronic design automation tools
    Patent number: 7904852
    Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: March 8, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eitan Cadouri, Krzysztof A. Kozminski, Haifang Liao, Kenneth Mednick, Roland Ruehl, Mark A. Snowden
  • Method and system for implementing parallel processing of electronic design automation tools
    Patent number: 7823095
    Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: October 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eitan Cadouri, Krzysztof A. Kozminski, Haifang Liao, Kenneth Mednick, Roland Ruehl, Mark A. Snowden
  • IC layout physical verification method
    Patent number: 7243321
    Abstract: Responding to a single command, a layout versus schematic (LVS) tool processes layout data describing positions of conductors on layers of an IC to produce data representing a shape recognition layer depicting boundary shapes of spirals of drawn inductors. The boundary shape of a spiral is the shape of the spiral as viewed from above with all of the layers of conductive material forming the spiral superimposed. The LVS tool then processes the shape recognition layer data to identify the type and position of each drawn inductor, to determine whether each inductor's spiral turns are of uniform width and spacing, to detect connectivity violations, and to determine parameters relating to the shape of the spiral from which its inductance can be computed.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: July 10, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaojun Wang, Kenneth Mednick
  • IC layout physical verification method
    Publication number: 20050229126
    Abstract: Responding to a single command, a layout versus schematic (LVS) tool processes layout data describing positions of conductors on layers of an IC to produce data representing a shape recognition layer depicting boundary shapes of spirals of drawn inductors. The boundary shape of a spiral is the shape of the spiral as viewed from above with all of the layers of conductive material forming the spiral superimposed. The LVS tool then processes the shape recognition layer data to identify the type and position of each drawn inductor, to determine whether each inductor's spiral turns are of uniform width and spacing, to detect connectivity violations, and to determine parameters relating to the shape of the spiral from which its inductance can be computed.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 13, 2005
    Inventors: Xiaojun Wang, Kenneth Mednick