Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Abstract: Semiconductor process excursions may be monitored by fabricating functional circuitry on a plurality of semiconductor devices and then testing the functional circuitry of the plurality of semiconductor devices using a sequence of test patterns. A cumulative failure curve may be determined that has points of discontinuity based on results of testing with the sequence of test patterns. A point of discontinuity magnitude at a selected location in the cumulative failure curve may be compared to an expected discontinuity magnitude. Process excursion analysis may be indicated when a point of discontinuity magnitude exceeds an expected magnitude threshold.

Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Abstract: Semiconductor process excursions may be monitored by fabricating functional circuitry on a plurality of semiconductor devices and then testing the functional circuitry of the plurality of semiconductor devices using a sequence of test patterns. A cumulative failure curve may be determined that has points of discontinuity based on results of testing with the sequence of test patterns. A point of discontinuity magnitude at a selected location in the cumulative failure curve may be compared to an expected discontinuity magnitude. Process excursion analysis may be indicated when a point of discontinuity magnitude exceeds an expected magnitude threshold.

Abstract: Methods and apparatus for analyzing an integrated circuit are disclosed. An example method includes supplying power to an on-chip supply power regulator of integrated circuit, instructing the on-chip supply power regulator to output a circuit supply signal having a desired minimum voltage level for the integrated circuit, instructing the integrated circuit to initiate an on-chip self-test process, analyzing the results of the on-chip self-test process, and repeating the process after stepping down the voltage of the circuit supply signal level.

Abstract: Methods and apparatus for analyzing an integrated circuit are disclosed. An example method includes supplying power to an on-chip supply power regulator of integrated circuit, instructing the on-chip supply power regulator to output a circuit supply signal having a desired minimum voltage level for the integrated circuit, instructing the integrated circuit to initiate an on-chip self-test process, analyzing the results of the on-chip self-test process, and repeating the process after stepping down the voltage of the circuit supply signal level.

Abstract: Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein.

Abstract: Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein.