Abstract: A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.

Abstract: A method and means for selectively stopping the internal clock of a microprocessor on any of 16 phases using functional components which include: a clock multiplier circuit, that receives a clock signal input from an external oscillator or other appropriate source, and outputs the internal clock signal for the microprocessor; control logic circuitry for processing and inputting stop signals to the clock multiplier; and a clock special purpose register, which provides control signals to the control logic circuitry to determine when stopping of the internal clock signal should occur.