Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: The electronic properties of molecular junctions of the general type carbon/molecule/TiO2/Au as examples of “molecular heterojunctions” consisting of a molecular monolayer and a semiconducting oxide. Junctions containing fluorene bonded to pyrolyzed photoresist film (PPF) were compared to those containing Al2O3 instead of fluorene, and those with only the TiO2 layer. The responses to voltage sweep and pulse stimulation were strongly dependent on junction composition and temperature. A transient current response lasting a few milliseconds results from injection and trapping of electrons in the TiO2 layer, and occurred in all three junction types studied. Conduction in PPF/TiO2/Au junctions is consistent with space charge limited conduction at low voltage, then a sharp increase in current once the space charge fills all the traps. With fluorene present, there is a slower, persistent change in junction conductance which may be removed by a reverse polarity pulse.

Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory ("DRAM") device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ("ZBT"), or pipeline burst static random access memory ("SRAM") devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a "Wait" pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater.