Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect; and a first receiver to receive second information comprising parameter information of at least one of the plurality of devices from the interconnect. The host controller may further include an integrity control circuit to receive the parameter information of the at least one of the plurality of devices and dynamically update at least one capability of the host controller based at least in part on the parameter information. Other embodiments are described and claimed.

Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

Abstract: In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

Abstract: In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

Abstract: In one embodiment, a host controller includes a read controller to adjust internal clock timing based on a timer value associated with a first device and communicate information on an interconnect with the first device according to the adjusted clock timing. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure may relate to an I3C bus master that is to identify that an I3C bus with which the I3C bus master is coupled is to enter a serial peripheral interface (SPI) high data rate (HDR) mode. The I3C bus master may be further to communicate, in accordance with the SPI HDR mode, with an SPI slave device via an I3C serial data (SDA) line, an I3C serial clock (SCL) line, and a selection line. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.

Abstract: In an embodiment, a host device includes: a transceiver to communicate information on an interconnect; a controller to control operation of the transceiver and to be a master for the interconnect; and a role transfer logic to cause a secondary device to be the master for the interconnect when at least a portion of the host device is to enter into a low power. Other embodiments are described and claimed.

Abstract: In one embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect; and a first receiver to receive second information comprising parameter information of at least one of the plurality of devices from the interconnect. The host controller may further include an integrity control circuit to receive the parameter information of the at least one of the plurality of devices and dynamically update at least one capability of the host controller based at least in part on the parameter information. Other embodiments are described and claimed.

Abstract: A magnetometer unit which may be incorporated in an electronic device receives first magnetic response data from a first magnetic sensor and second magnetic response data from a second magnetic sensor displaced from the first magnetic sensor. The magnetometer unit generates a composite response surface representation from the first magnetic response data and the second magnetic response data, and stores the composite response surface representation in a non-transitory memory.

Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

Abstract: In one example a magnetometer unit comprises logic to receive first magnetic response data from a first magnetic sensor and second magnetic response data from a second magnetic sensor displaced from the first magnetic sensor, generate a composite response surface representation from the first magnetic response data and the second magnetic response data, and store the composite response surface representation in a non-transitory memory. Other examples may be described.