Patents by Inventor Kenneth P. Tumin

Kenneth P. Tumin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Design-for-test circuit for low pin count devices
    Patent number: 7274203
    Abstract: A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: September 25, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kenneth P. Tumin, George E. Baker, Dale J. McQuirk, Matthew G. Stout
  • Methods of simulating an electronic circuit design
    Patent number: 6021271
    Abstract: A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: February 1, 2000
    Assignee: Motorola, Inc.
    Inventors: Marlan L. Winter, Kenneth P. Tumin, Steven P. Lindquist
  • Method of forming an integrated circuit
    Patent number: 5805862
    Abstract: A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: September 8, 1998
    Assignee: Motorola, Inc.
    Inventors: Marlan L. Winter, Kenneth P. Tumin, Steven P. Lindquist
  • Methods of simulating an electronic circuit design and forming an integrated circuit
    Patent number: 5781760
    Abstract: During an electronic circuit simulation, an input file is generated that has source code and stimulus sections. Each of the source code and stimulus sections includes linking portions that each link a portion of the source code to a portion of the stimulus sections. The input file is processed to generate object code and a stimulus file that includes linking portions. The linking portions of the stimulus file allow events to occur that are synchronized with the object code during the running of a simulation program. The linking between the stimulus file and the object code is synchronized because the stimulus file is generated from the input file that has the linking portions. The linking remains synchronized even if the input file is modified. After a simulation, masks (30, 40, 50, 60, 70) can be generated and used to form an integrated circuit (20).
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: July 14, 1998
    Assignee: Motorola, Inc.
    Inventors: Marlan L. Winter, Kenneth P. Tumin, Steven P. Lindquist