Patents by Inventor Kenneth Paist
Kenneth Paist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8300684Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.Type: GrantFiled: June 29, 2009Date of Patent: October 30, 2012Assignee: LSI CorporationInventors: Mohammad Mobin, Ye Liu, Kenneth Paist, Mark Trafford
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Patent number: 8243782Abstract: In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication).Type: GrantFiled: June 29, 2009Date of Patent: August 14, 2012Assignee: LSI CorporationInventors: Mohammad Mobin, Ye Liu, Kenneth Paist, Mark Trafford
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Patent number: 7948914Abstract: In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area.Type: GrantFiled: January 28, 2009Date of Patent: May 24, 2011Assignee: Agere Systems Inc.Inventors: Kouros Azimi, Mohammad Mobin, Roger Fratti, Sailesh Merchant, Kenneth Paist
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Publication number: 20100329322Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Inventors: Mohammad Mobin, Ye Liu, Kenneth Paist, Mark Trafford
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Publication number: 20100329325Abstract: In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication).Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Inventors: Mohammad Mobin, Ye Liu, Kenneth Paist, Mark Trafford
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Publication number: 20100188987Abstract: In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Applicant: Agere Systems, Inc.Inventors: Kouros Azimi, Roger Fratti, Sailesh Merchant, Mohammad Mobin, Kenneth Paist
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Publication number: 20050040893Abstract: Frequency spectrum spreading of a timing recovery circuit, such as a PLL, is controlled by periodically calculating each value for a divisor, M, of a fractional divider in the feedback path of the PLL. The fractional divider divides the output signal of a voltage-controlled oscillator (VCO) of the PLL by the divisor, M, and the value for divisor, M, is periodically updated based on a spreading profile. The output of the fractional divider and a reference clock signal are provided to a phase detector of the PLL so as to cause the PLL to slew the output frequency of the PLL in accordance with the spreading profile.Type: ApplicationFiled: August 20, 2003Publication date: February 24, 2005Inventors: Kenneth Paist, Parag Parikh
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Patent number: 6389090Abstract: For a digital communications receiver, a clock and data signal recovery circuit and method use an all digital delay locked loop timed by an on-chip transmit clock signal. The digital delay locked loop includes a phase detector and loop filter. The phase detector determines, for each data signal rising or falling edge, if the current delay of a reference clock signal leads or lags the data signal edge. The loop filter examines the stream of such lead/lag indications, performs a nonlinear filtering process thereon, and in response increases or decreases the clock signal phase appropriately.Type: GrantFiled: February 6, 1998Date of Patent: May 14, 2002Assignee: 3Com CorporationInventors: Anthony E. Zortea, Kenneth Paist
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Publication number: 20010038675Abstract: For a digital communications receiver, a clock and data signal recovery circuit and method use an all digital delay locked loop timed by an on-chip transmit clock signal. The digital delay locked loop includes a phase detector and loop filter. The phase detector determines, for each data signal rising or falling edge, if the current delay of a reference clock signal leads or lags the data signal edge. The loop filter examines the stream of such lead/lag indications, performs a nonlinear filtering process thereon, and in response increases or decreases the clock signal phase appropriately.Type: ApplicationFiled: February 6, 1998Publication date: November 8, 2001Inventors: ANTHONY E. ZORTEA, KENNETH PAIST
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Patent number: 5809072Abstract: An equalizer receives an analog input signal and filters the signal to undistort the input signal. A converter stage converts the analog input signal into a digital output signal for use in a digital system. A bit sequence indicator analyzes the structure of the digital output signal to determine whether any errors have occurred in transmission and conversion. An adaptor state machine causes the modification of the analog signal based on a feedback loop including information on the errors detected in the packets of digital signals, rather than the analog data itself.Type: GrantFiled: March 15, 1996Date of Patent: September 15, 1998Assignee: Integrated Circuit SystemsInventors: Anthony E. Zortea, James McGough, Kenneth Paist