Abstract: Provided are polynucleotides encoding inactivated cell surface receptors. Also provided are genetically engineered induced pluripotent stem cells (iPSCs) and derivative cells thereof expressing a chimeric antigen receptor (CAR) and methods of using the same. Also provided are compositions, polypeptides, vectors, and methods of manufacturing.

Abstract: Provided are polynucleotides encoding inactivated cell surface receptors. Also provided are genetically engineered induced pluripotent stem cells (iPSCs) and derivative cells thereof expressing a chimeric antigen receptor (CAR) and methods of using the same. Also provided are compositions, polypeptides, vectors, and methods of manufacturing.

Abstract: A digital pulse width modulation driver system and method can include: receiving input digital data with a digital signal processing chip on a device; converting the input digital data into pulse width modulated data; generating an amplitude signal with the digital signal processing chip; transmitting the amplitude signal and the pulse width modulated data from a transmit interface within the device to a receive interface within an analog driver chip; and amplifying the pulse width modulated data with a driver coupled to a high voltage rail based on the amplitude signal corresponding to the high voltage rail, or amplifying the pulse width modulated data with the driver coupled to a low voltage rail based on the amplitude signal corresponding to the low voltage rail.

Abstract: A system, method, and apparatus for pulsed charging applications comprises a bulk capacitor operably connected to a power source, an inductor connected to the bulk capacitor with a charge switch, a pulse capacitor connected to the inductor, a freewheeling diode connecting a point between the charge switch and the inductor to a point after the pulse capacitor, a second diode connecting the inductor to the pulse capacitor, and a pulse switch connecting the pulse capacitor to a load.

Abstract: A digital pulse width modulation driver system and method can include: receiving input digital data with a digital signal processing chip on a device; converting the input digital data into pulse width modulated data; generating an amplitude signal with the digital signal processing chip; transmitting the amplitude signal and the pulse width modulated data from a transmit interface within the device to a receive interface within an analog driver chip; and amplifying the pulse width modulated data with a driver coupled to a high voltage rail based on the amplitude signal corresponding to the high voltage rail, or amplifying the pulse width modulated data with the driver coupled to a low voltage rail based on the amplitude signal corresponding to the low voltage rail.

Abstract: A system, method, and apparatus for pulsed charging applications comprises a bulk capacitor operably connected to a power source, an inductor connected to the bulk capacitor with a charge switch, a pulse capacitor connected to the inductor, a freewheeling diode connecting a point between the charge switch and the inductor to a point after the pulse capacitor, a second diode connecting the inductor to the pulse capacitor, and a pulse switch connecting the pulse capacitor to a load.

Abstract: Unique cervical collars and patient interfaces for sleep apnea therapy. One cervical collar features a chin-supporting member whose topside is movable relative to a chest-abutting member. The top side is biased upwardly against the underside of the wearer's chin to maintain an erect head position and closed lower jaw position when the user is asleep, while allowing intentional opening of the mouth during consciousness. The chest-abutting member features a support by which a patient interface is carried thereon to avoid or reduce the need for a separate head-worn securing means. A patient interface employs a venturi-like airway configuration to create a vacuum for securing the patient interface to facial or nasal tissue without head straps or the like. Electrical contacts on the cervical collar detect a positional status of the wearer's lower jaw, and are used to control an operational state of a pressurized air source coupled to the interface.

Abstract: A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout?). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor.

Abstract: A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout?). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor.

Abstract: A low voltage controller includes a circuit board having first and second lengthwise ends and having a high voltage input proximate the first end and a high voltage output proximate the second end, the high voltage input for receiving an AC high voltage, a voltage conversion circuit disposed on the circuit board between the first and second ends and including a step-down transformer, the voltage conversion circuit being structured for converting the AC high voltage to at least one DC low voltage, a power terminal, at least one load switch disposed on the circuit board and activated by use of the at least one DC low voltage for controllably switching the AC high voltage from the power terminal to a first output of the high voltage output, and a hot wire providing an electrical connection for transferring the AC high voltage from the high voltage input to the power terminal.

Abstract: An apparatus for containing oil spills or the likes in a body of water. The apparatus is formed of high strength lightweight plastic material. The apparatus is filled by air and water so as to automatically move to a vertical position in the body of contaminated water and provide a barrier to contain an oil spill. The barrier uses water as ballast.