Abstract: A method for generating test patterns for testing digital electronic circuits, whereby a test pattern template is defined that fully specifies some primary inputs while other primary inputs are specified in accordance with selected series of codes. The test pattern template is then repeatedly converted into a stimulus pattern using different integers in the selected series of codes, and fault simulation is performed on a circuit under test using each stimulus pattern. A stimulus pattern is then saved for subsequent testing of the circuit under test whenever fault simulation using that stimulus pattern shows that fault coverage has increased. The method significantly reduces the number of primary input combinations required for generating test patterns.