Abstract: A programmable control unit for disk memory and controller comprising a microprocessor (MPU), random access memory (RAM) used as a buffer to cache disk resident data used by a data processing system (DPS), and a configurable data path (CDP) which couples the DPS to the disk controller. The (MPU) is programmed to provide the DPS rapid access to disk resident data by so controlling the CDP as to maintain a memory cache of disk resident data in the RAM. Data is cached under either directed control via an application level task or operator console directive, or under dynamic control through which a predetermined number of successive blocks of data are read from the disk and stored in the RAM each time any one block is addressed, and once the RAM is full, by discarding from the RAM a block of data which the immediate history has shown is least useful.

Abstract: A method and apparatus for addressing memory locations in a random access memory system having m address lines and 2 Exp(m+n) address locations. The random access memory system is divided into a plurality of 2 Exp(n) memory modules, each memory module having 2 Exp(m) memory locations. Each of the memory modules is divided into 2 Exp(n) groups of 2 Exp(m-n) memory locations. In a specific embodiment in which m=15 and n=4, each memory module contains 2 Exp(15) or 32,768 address locations, and the sixteen memory modules together contain 524,288 address locations. Each memory module is divided into 2 Exp(4) or sixteen groups of memory locations. The first or most significant 4 bits of a 15 bit address word are used to address one of the sixteen groups of memory locations and also to address a particular memory module containing the addressed group.