Abstract: A digital system bus arbiter network which provides prioritized but equal opportunity for various devices to gain access to a common bus. The network samples the state of all pending requests for bus access, stores the current requests and generates a sequence of bus access granting signals in an order determined by the priority of the stored bus requests. When all of the bus requests have been processed for a given sample period, the network resamples currently pending bus requests and repeats the process of generating the sequence of bus granting signals on a prioritized basis. The network guarantees an equal share of bus bandwidth to each device.