Abstract: A bias circuit for preventing excessive emission from light emitting diodes includes a switch connected to power. A light emitting diode connects to the switch output. Two bias current legs, electrically connected in parallel, interpose the light emitting diode and ground. A fault comparator connects to the bias current legs and a logic OR gate. Four fault comparators can be implemented, each detecting a unique fault condition. The logic OR gate has an output connected to the input of the switch.

Abstract: A bias circuit for preventing excessive emission from light emitting diodes includes a switch connected to power. A light emitting diode connects to the switch output. Two bias current legs, electrically connected in parallel, interpose the light emitting diode and ground. A fault comparator connects to the bias current legs and a logic OR gate. Four fault comparators can be implemented, each detecting a unique fault condition. The logic OR gate has an output connected to the input of the switch.

Abstract: An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Abstract: According to the invention, the electrical charge which is transferred to a circuit node by the switching ON or OFF of a field effect transistor whose source or drain is connected to that node is cancelled by connecting the source and drain of another field effect transistor to that circuit node and applying to its gate terminal a complement of the switching signal applied to the gate electrode of the first field effect transistor.