Abstract: In an example, a component analyzer can compute a respective part score for each part of the platform based on a part property table, and a respective connection score for each connection of the platform based on a connection property table. The component analyzer can provide the respective part and connection scores as score data to an architecture modeling engine to compute a probability model based on the score data and an architecture model. The probability model can include a part probability value and a connection probability value, and the architecture model can characterize a target architecture of the platform. A survivability analysis engine can evaluate the probability model and the architecture model to determine a likelihood that one or more potential cyber-attacks on the platform based on the target architecture are successful or unsuccessful in compromising at least one part of the platform.

Abstract: A system and related method for determining whether an electrical circuit has been compromised. The system includes a circuit probe positioned relative to the electrical circuit that detects electromagnetic circuit emissions therefrom and an analysis device electrically coupled to the circuit probe and receiving electromagnetic emissions detection signals therefrom, where the analysis device identifies constituent frequencies and their magnitudes in the detection signals. The system also includes a comparison processor responsive to the constituent frequencies and magnitudes from the analysis device, where the comparison processor compares the constituent frequencies and magnitudes to previously stored constituent frequencies and magnitudes obtained from an equivalent test circuit to the electrical circuit to determine whether the electrical circuit has been compromised. A background probe can be provided to obtain background emissions that can be subtracted from the circuit emissions.

Abstract: A system and related method for determining whether an electrical circuit has been compromised. The system includes a circuit probe positioned relative to the electrical circuit that detects electromagnetic circuit emissions therefrom and an analysis device electrically coupled to the circuit probe and receiving electromagnetic emissions detection signals therefrom, where the analysis device identifies constituent frequencies and their magnitudes in the detection signals. The system also includes a comparison processor responsive to the constituent frequencies and magnitudes from the analysis device, where the comparison processor compares the constituent frequencies and magnitudes to previously stored constituent frequencies and magnitudes obtained from an equivalent test circuit to the electrical circuit to determine whether the electrical circuit has been compromised. A background probe can be provided to obtain background emissions that can be subtracted from the circuit emissions.

Abstract: A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.

Abstract: A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal amounts of time in each mode over the system's lifecycle. A bi-directional data bus inverter is positioned between a system processor and volatile memory. When the system is running in inversion mode, data from non-volatile memory is inverted (0's and 1's are swapped) when copied to volatile memory, and the data bus inverter rectifies all data bits flowing in/out of the processor. By balancing the time spent by individual memory addresses in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as internal processor cache memory, and FPGA configuration memory, is also disclosed.

Abstract: A field programmable gate array (FPGA) including a root of trust architecture. The architecture includes a system controller providing system control commands for the architecture and a cryptography processor for performing a hash or key operation for authentication of controller-embedded software and attestation of correct firmware in external system resources. The architecture also includes a lock-step fault-tolerant processor being responsive to messages from the system controller, and including a plurality of soft lock-step cores. Each soft core including separate memory and resources and operating on the same input, where each soft core provides output messages that are analyzed by a logic in the fault-tolerant processor that selects one of the messages to be output to the cryptography processor.

Abstract: A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal amounts of time in each mode over the system's lifecycle. A bi-directional data bus inverter is positioned between a system processor and volatile memory. When the system is running in inversion mode, data from non-volatile memory is inverted (0's and 1's are swapped) when copied to volatile memory, and the data bus inverter rectifies all data bits flowing in/out of the processor. By balancing the time spent by individual memory addresses in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as internal processor cache memory, and FPGA configuration memory, is also disclosed.

Abstract: A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.

Abstract: In one embodiment, a method and apparatus for analyzing a design of an integrated circuit (IC) are disclosed. For example, the method parses a netlist file of the IC where a module of the IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure. The method traces through a connectivity of the plurality of sub-modules, and tabulates data associated with the connectivity with a fault cost associated with a structure of the IC.