Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.