Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Abstract: The present disclosure relates to routing superconducting wires in superconducting circuits and in particular to efficiently routing superconducting wires that meet inductance requirements. The superconducting wire routing technique involves modeling the target location not only as a physical location, but as a physical location (e.g., x, y, and z dimensions) combined with inductance (e.g., a target inductance range). One or more other constraints may also be included in the modeling, such as a number of wires that would need to be moved/lifted, a number of circuit-vias allowing passage through layers of the circuit, an amount of cross-coupling with other inductors, and a number of wire segments.

Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.

Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Abstract: A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.

Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Abstract: A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.

Abstract: The present disclosure relates to routing superconducting wires in superconducting circuits and in particular to efficiently routing superconducting wires that meet inductance requirements. The superconducting wire routing technique involves modeling the target location not only as a physical location, but as a physical location (e.g., x, y, and z dimensions) combined with inductance (e.g., a target inductance range). One or more other constraints may also be included in the modeling, such as a number of wires that would need to be moved/lifted, a number of circuit-vias allowing passage through layers of the circuit, an amount of cross-coupling with other inductors, and a number of wire segments.

Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.

Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint.

Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint.

Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.