Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A doped photovoltaic device is presented. The photovoltaic device includes a semiconductor absorber layer or stack disposed between a front contact and a back contact. The absorber layer comprises cadmium, selenium, and tellurium doped with Ag, and optionally with Cu. The Ag dopant may be added to the absorber in amounts ranging from 5×1015/cm3 to 2.5×1017/cm3 via any of several methods of application before, during, or after deposition of the absorber layer. The photovoltaic device has improved Fill Factor and PMAX at higher Pr(=Isc*Voc product) values, e.g. about 160 W, which results in improved conversion efficiency compared to a device not doped with Ag. Improved PT may result from increased Isc, increased Voc, or both.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A doped photovoltaic device is presented. The photovoltaic device includes a semiconductor absorber layer or stack disposed between a front contact and a back contact. The absorber layer comprises cadmium, selenium, and tellurium doped with Ag, and optionally with Cu. The Ag dopant may be added to the absorber in amounts ranging from 5×1015/cm3 to 2.5×1017/cm3 via any of several methods of application before, during, or after deposition of the absorber layer. The photovoltaic device has improved Fill Factor and PMAX at higher Pr (=Isc*Voc product) values, e.g. about 160 W, which results in improved conversion efficiency compared to a device not doped with Ag. Improved PT may result from increased Isc, increased Voc, or both.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of the base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.