Patents by Inventor Kenneth Robert Willis

Kenneth Robert Willis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10726188
    Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Taranjit Singh Kukal, Rameet Pal, Bradford Griffin, Kenneth Robert Willis, Hui Qi, Xuegang Zeng
  • Patent number: 10496767
    Abstract: The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse response characterization, wherein the random input pattern is based upon, at least in part, an electronic circuit simulation associated with the electronic circuit design.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Hui Qi, Kenneth Robert Willis, Xuegang Zeng
  • Patent number: 10380292
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (“FDTD”) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kenneth Robert Willis, Jing Wang, Hui Qi, Xuegang Zeng, Zhen Mu
  • Patent number: 9798848
    Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 24, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Taranjit Singh Kukal, Rameet Pal, Bradford Griffin, Kenneth Robert Willis, Hui Qi, Xuegang Zeng