Patents by Inventor Kenneth Rovers
Kenneth Rovers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210358080Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation: (1) P=?(C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=?(C2<<8)+128.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventor: Kenneth Rovers
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Publication number: 20210295588Abstract: A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p<n; and control logic configured to allocate blocks of encoded texture data to the decoders in accordance with the texel request.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Inventors: Yoong Chert Foo, Kenneth Rovers
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Patent number: 11113786Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation: (1) P=?((C2«8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=?((C2«8)+128.Type: GrantFiled: December 20, 2019Date of Patent: September 7, 2021Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Patent number: 11043020Abstract: A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p<n; and control logic configured to allocate blocks of encoded texture data to the decoders in accordance with the texel request.Type: GrantFiled: March 2, 2020Date of Patent: June 22, 2021Assignee: Imagination Technologies LimitedInventors: Yoong Chert Foo, Kenneth Rovers
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Publication number: 20210184693Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: ApplicationFiled: December 31, 2020Publication date: June 17, 2021Inventor: Kenneth Rovers
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Publication number: 20210150777Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Inventors: Kenneth Rovers, Yoong Chert Foo
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Publication number: 20210132902Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew?1),bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: ApplicationFiled: January 5, 2021Publication date: May 6, 2021Inventor: Kenneth Rovers
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Patent number: 10937198Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.Type: GrantFiled: April 28, 2018Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventors: Kenneth Rovers, Yoong Chert Foo
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Patent number: 10886942Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: GrantFiled: July 16, 2020Date of Patent: January 5, 2021Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Patent number: 10884702Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min {(ew?1), bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: GrantFiled: May 18, 2020Date of Patent: January 5, 2021Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Publication number: 20200350925Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: ApplicationFiled: July 16, 2020Publication date: November 5, 2020Inventor: Kenneth Rovers
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Publication number: 20200278834Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min {(ew?1), bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventor: Kenneth Rovers
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Patent number: 10756754Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: GrantFiled: January 9, 2020Date of Patent: August 25, 2020Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Publication number: 20200202582Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128.64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.Type: ApplicationFiled: December 20, 2019Publication date: June 25, 2020Inventor: Kenneth Rovers
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Publication number: 20200202489Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation: (1) P=?((C2«8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=?((C2«8)+128.Type: ApplicationFiled: December 20, 2019Publication date: June 25, 2020Inventor: Kenneth Rovers
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Publication number: 20200202607Abstract: A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p<n; and control logic configured to allocate blocks of encoded texture data to the decoders in accordance with the texel request.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Yoong Chert Foo, Kenneth Rovers
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Patent number: 10691411Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew?1), bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: GrantFiled: January 4, 2020Date of Patent: June 23, 2020Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Publication number: 20200153453Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-11, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: ApplicationFiled: January 9, 2020Publication date: May 14, 2020Inventor: Kenneth Rovers
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Publication number: 20200142668Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew ?1), bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: ApplicationFiled: January 4, 2020Publication date: May 7, 2020Inventor: Kenneth Rovers
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Patent number: 10636195Abstract: A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p<n; and control logic configured to allocate blocks of encoded texture data to the decoders in accordance with the texel request.Type: GrantFiled: April 28, 2018Date of Patent: April 28, 2020Assignee: Imagination Technologies LimitedInventors: Yoong Chert Foo, Kenneth Rovers